| Message ID | 20240111-sm8150-dfs-support-v2-2-6edb44c83d3b@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 4b3dbd706a6181f19ba63f9265e6f996f01aa76d |
| Headers | show |
| Series | clk: qcom: Add dfs support for QUPv3 RCGs on SM8150 | expand |
On 11/01/2024 07:32, Satya Priya Kakitapalli wrote: > Add gcc video axic, axi0 and axi1 resets for the global clock controller > on sm8150. > > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index dfefd5e8bf6e..921a33f24d33 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -239,6 +239,9 @@ #define GCC_USB30_PRIM_BCR 26 #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +#define GCC_VIDEO_AXIC_CLK_BCR 29 +#define GCC_VIDEO_AXI0_CLK_BCR 30 +#define GCC_VIDEO_AXI1_CLK_BCR 31 /* GCC GDSCRs */ #define PCIE_0_GDSC 0
Add gcc video axic, axi0 and axi1 resets for the global clock controller on sm8150. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> --- include/dt-bindings/clock/qcom,gcc-sm8150.h | 3 +++ 1 file changed, 3 insertions(+)