From patchwork Thu Jan 25 19:38:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paloma Arellano X-Patchwork-Id: 13531608 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9991A135407 for ; Thu, 25 Jan 2024 19:39:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706211548; cv=none; b=hdl4S9mWHjYBNcCTWYT90ArMSTGj5YHeyMaAkO+oaG0P0h3vgSs0IA+9OmEvAzmSbA/PK3DwqBt0n1O7Lhl9+D2+ti7Gj5/aVTt8IlRhFeK5ebFo3veV7p1FBHm13xdCnnSt2Cn5yS2+Na+h5GOspOd/K4q8NWF8II5v2DVhXCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706211548; c=relaxed/simple; bh=+Hh1e0RhlkJIpdhk2A451ZbdV8jLa9CtcB0vzaH9TWU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cjySSuqhIkgN7qf2aCd44Z6ZEVbQDBIfTBEyu4cSPSdM/5+I0snLpjyucW+k9XEUhDaSAtTjyrFwnS3rHwxhpQYIgduR/YFO+xbaXszkRCk4oDd/hhlKbQyGkCr4jVZzePYy8wjSeUSHMMpgQfnYb1IBJuq4gG7OeeCWIbBuKbU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=heHSJ8WP; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="heHSJ8WP" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40PJFIBQ012049; Thu, 25 Jan 2024 19:39:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=YolNAg8II2/yKwZ2ARqLv5TKOxZcfQG3j4Kp3FqDjng=; b=he HSJ8WPPCEsXKr5oEQwCSBWFLFDRh2219JAaKBUaNKIJggRbT1LR2kMeSn29Dz0SP 4PYb1sguWrmi9VjtYC2ktgfu7reYEy6js2k93AUdjHhh1rpDsp6JgLXhuPll9ZGE GSWJJ/OVSn8pbyOCjZvkhSw9ZnI+umEVQSGMklvwsPZvYyaOkue0jbG5yXcrDi3s Al/C0zbC/MvkZqw6/2TK/8kBENIzunv4cwZKDqaW7j1XSMelXxVvix5QdvKTZ5xS p+W8hQRiy1snRJhD3jF2VkszpVJ25Lj1rOKm0SlwDsUUb5cTA0GJ1NF1tiycBTQa 5JUIaF1ZjcLhEeTeSb4A== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vuqra12gk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jan 2024 19:39:00 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40PJd0oY002387 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jan 2024 19:39:00 GMT Received: from hu-parellan-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 25 Jan 2024 11:38:59 -0800 From: Paloma Arellano To: CC: Paloma Arellano , , , , , , , , , , , Subject: [PATCH 04/17] drm/msm/dp: store mode YUV420 information to be used by rest of DP Date: Thu, 25 Jan 2024 11:38:13 -0800 Message-ID: <20240125193834.7065-5-quic_parellan@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240125193834.7065-1-quic_parellan@quicinc.com> References: <20240125193834.7065-1-quic_parellan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: zRIirZ9oRFhrjtRIgTt79J3EWSwdHQKr X-Proofpoint-ORIG-GUID: zRIirZ9oRFhrjtRIgTt79J3EWSwdHQKr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-25_12,2024-01-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 malwarescore=0 mlxscore=0 impostorscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2401250142 Wide bus is not supported when the mode is YUV420 in DP. In preparation for changing the DPU programming to reflect this, the value and assignment location of wide_bus_en for the DP submodules must be changed. Move it from boot time in dp_init_sub_modules() to run time in dp_display_mode_set. Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 17 +++++++++++++---- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 9df2a8b21021e..ddac55f45a722 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -784,10 +784,6 @@ static int dp_init_sub_modules(struct dp_display_private *dp) goto error_ctrl; } - /* populate wide_bus_supported to different layers */ - dp->ctrl->wide_bus_en = dp->wide_bus_supported; - dp->catalog->wide_bus_en = dp->wide_bus_supported; - return rc; error_ctrl: @@ -808,6 +804,7 @@ static int dp_display_set_mode(struct msm_dp *dp_display, drm_mode_copy(&dp->panel->dp_mode.drm_mode, &mode->drm_mode); dp->panel->dp_mode.bpp = mode->bpp; dp->panel->dp_mode.capabilities = mode->capabilities; + dp->panel->dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420; dp_panel_init_panel_info(dp->panel); return 0; } @@ -1402,6 +1399,9 @@ bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) dp = container_of(dp_display, struct dp_display_private, dp_display); + if (dp->dp_mode.out_fmt_is_yuv_420) + return false; + return dp->wide_bus_supported; } @@ -1615,6 +1615,15 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge, dp_display->dp_mode.h_active_low = !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); + + dp_display->dp_mode.out_fmt_is_yuv_420 = + drm_mode_is_420_only(&dp->connector->display_info, adjusted_mode); + + /* populate wide_bus_support to different layers */ + dp_display->ctrl->wide_bus_en = + dp_display->dp_mode.out_fmt_is_yuv_420 ? false : dp_display->wide_bus_supported; + dp_display->catalog->wide_bus_en = + dp_display->dp_mode.out_fmt_is_yuv_420 ? false : dp_display->wide_bus_supported; } void dp_bridge_hpd_enable(struct drm_bridge *bridge) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index a0dfc579c5f9f..6ec68be9f2366 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -19,6 +19,7 @@ struct dp_display_mode { u32 bpp; u32 h_active_low; u32 v_active_low; + bool out_fmt_is_yuv_420; }; struct dp_panel_in {