| Message ID | 20240131102003.2061203-1-amadeus@jmu.edu.cn (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/3] arm64: dts: qcom: ipq6018: separate CPU OPP tables | expand |
On Wed, 31 Jan 2024 at 12:22, Chukun Pan <amadeus@jmu.edu.cn> wrote: > > Some IPQ6000 SoCs do not come with PMIC (MP5496) chip, > which causes cpufreq to be unavailable due to lack of > cpu-supply. Separate CPU OPP tables from soc.dtsi to > support versions with and without PMIC chip. I went on and checked ipq6018.dtsi. It will need to be reworked before we can continue with PMIC-less devices. Obviously, the PMIC is not a part of the SoC. So please move the "qcom,rpm-mp5496-regulators" node to the board files together with the cpu-supply properties that reference that regulator. The SoC itself supports all listed frequencies, so it is incorrect to split the opp tables from the ipq6018.dtsi. Instead please patch the PMIC-less boards in the following way: #include "ipq6018.dtsi" &cpu_opp_table { /* the board doesn't have a PMIC, disable CPU frequencies which require higher voltages */ /delete-node/ opp-1320000000; /delete-node/ opp-1440000000; }; > > Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> > --- > arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 + > arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi | 74 ++++++++++++++++++++ > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 56 --------------- > 3 files changed, 75 insertions(+), 56 deletions(-) > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > index f5f4827c0e17..06dfc2cb6b7f 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > @@ -8,6 +8,7 @@ > /dts-v1/; > > #include "ipq6018.dtsi" > +#include "ipq6018-opp.dtsi" > > / { > model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; > diff --git a/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi > new file mode 100644 > index 000000000000..9c0bed2d8bf5 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * IPQ60xx with PMIC (MP5496) CPU OPP tables > + */ > + > +/ { > + cpu_opp_table: opp-table-cpu { > + compatible = "operating-points-v2-kryo-cpu"; > + nvmem-cells = <&cpu_speed_bin>; > + opp-shared; > + > + opp-864000000 { > + opp-hz = /bits/ 64 <864000000>; > + opp-microvolt = <725000>; > + opp-supported-hw = <0xf>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1056000000 { > + opp-hz = /bits/ 64 <1056000000>; > + opp-microvolt = <787500>; > + opp-supported-hw = <0xf>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1320000000 { > + opp-hz = /bits/ 64 <1320000000>; > + opp-microvolt = <862500>; > + opp-supported-hw = <0x3>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1440000000 { > + opp-hz = /bits/ 64 <1440000000>; > + opp-microvolt = <925000>; > + opp-supported-hw = <0x3>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1608000000 { > + opp-hz = /bits/ 64 <1608000000>; > + opp-microvolt = <987500>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1800000000 { > + opp-hz = /bits/ 64 <1800000000>; > + opp-microvolt = <1062500>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + }; > +}; > + > +&CPU0 { > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&ipq6018_s2>; > +}; > + > +&CPU1 { > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&ipq6018_s2>; > +}; > + > +&CPU2 { > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&ipq6018_s2>; > +}; > + > +&CPU3 { > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&ipq6018_s2>; > +}; > diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > index 5e1277fea725..ea72fd5739ac 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > @@ -41,8 +41,6 @@ CPU0: cpu@0 { > next-level-cache = <&L2_0>; > clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > clock-names = "cpu"; > - operating-points-v2 = <&cpu_opp_table>; > - cpu-supply = <&ipq6018_s2>; > }; > > CPU1: cpu@1 { > @@ -53,8 +51,6 @@ CPU1: cpu@1 { > next-level-cache = <&L2_0>; > clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > clock-names = "cpu"; > - operating-points-v2 = <&cpu_opp_table>; > - cpu-supply = <&ipq6018_s2>; > }; > > CPU2: cpu@2 { > @@ -65,8 +61,6 @@ CPU2: cpu@2 { > next-level-cache = <&L2_0>; > clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > clock-names = "cpu"; > - operating-points-v2 = <&cpu_opp_table>; > - cpu-supply = <&ipq6018_s2>; > }; > > CPU3: cpu@3 { > @@ -77,8 +71,6 @@ CPU3: cpu@3 { > next-level-cache = <&L2_0>; > clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > clock-names = "cpu"; > - operating-points-v2 = <&cpu_opp_table>; > - cpu-supply = <&ipq6018_s2>; > }; > > L2_0: l2-cache { > @@ -95,54 +87,6 @@ scm { > }; > }; > > - cpu_opp_table: opp-table-cpu { > - compatible = "operating-points-v2-kryo-cpu"; > - nvmem-cells = <&cpu_speed_bin>; > - opp-shared; > - > - opp-864000000 { > - opp-hz = /bits/ 64 <864000000>; > - opp-microvolt = <725000>; > - opp-supported-hw = <0xf>; > - clock-latency-ns = <200000>; > - }; > - > - opp-1056000000 { > - opp-hz = /bits/ 64 <1056000000>; > - opp-microvolt = <787500>; > - opp-supported-hw = <0xf>; > - clock-latency-ns = <200000>; > - }; > - > - opp-1320000000 { > - opp-hz = /bits/ 64 <1320000000>; > - opp-microvolt = <862500>; > - opp-supported-hw = <0x3>; > - clock-latency-ns = <200000>; > - }; > - > - opp-1440000000 { > - opp-hz = /bits/ 64 <1440000000>; > - opp-microvolt = <925000>; > - opp-supported-hw = <0x3>; > - clock-latency-ns = <200000>; > - }; > - > - opp-1608000000 { > - opp-hz = /bits/ 64 <1608000000>; > - opp-microvolt = <987500>; > - opp-supported-hw = <0x1>; > - clock-latency-ns = <200000>; > - }; > - > - opp-1800000000 { > - opp-hz = /bits/ 64 <1800000000>; > - opp-microvolt = <1062500>; > - opp-supported-hw = <0x1>; > - clock-latency-ns = <200000>; > - }; > - }; > - > pmuv8: pmu { > compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > -- > 2.25.1 > >
Hi, Dmitry > I went on and checked ipq6018.dtsi. It will need to be reworked before > we can continue with PMIC-less devices. > Obviously, the PMIC is not a part of the SoC. So please move the > "qcom,rpm-mp5496-regulators" node to the board files together with the > cpu-supply properties that reference that regulator. Thanks a lot for your advice, now things are clearer. My idea is as follows: 1. Add all frequencies supported by SoCs in ipq6018.dtsi 2. Move cpu-supply and mp5496 nodes to ipq6018-mp5496.dtsi &CPU0 { cpu-supply = <&ipq6018_s2>; }; ... &rpm_requests { regulators { rpm-mp5496... ipq6018_s2... }; }; > The SoC itself supports all listed frequencies, so it is incorrect to > split the opp tables from the ipq6018.dtsi. Instead please patch the > PMIC-less boards in the following way: > #include "ipq6018.dtsi" > &cpu_opp_table { > /* the board doesn't have a PMIC, disable CPU frequencies which > require higher voltages */ > /delete-node/ opp-1320000000; > /delete-node/ opp-1440000000; >}; Thank you but no need. The CPUFreq NVMEM driver will give the CPU maximum frequency based on the cpu_speed_bin and opp-supported-hw. Thanks, Chukun
On Thu, 1 Feb 2024 at 05:08, Chukun Pan <amadeus@jmu.edu.cn> wrote: > > Hi, Dmitry > > I went on and checked ipq6018.dtsi. It will need to be reworked before > > we can continue with PMIC-less devices. > > > Obviously, the PMIC is not a part of the SoC. So please move the > > "qcom,rpm-mp5496-regulators" node to the board files together with the > > cpu-supply properties that reference that regulator. > > Thanks a lot for your advice, now things are clearer. > My idea is as follows: > > 1. Add all frequencies supported by SoCs in ipq6018.dtsi > > 2. Move cpu-supply and mp5496 nodes to ipq6018-mp5496.dtsi Straight to the board files, please, no need for additional includes. > > &CPU0 { > cpu-supply = <&ipq6018_s2>; > }; > ... > > &rpm_requests { > regulators { > rpm-mp5496... > ipq6018_s2... > }; > }; > > > The SoC itself supports all listed frequencies, so it is incorrect to > > split the opp tables from the ipq6018.dtsi. Instead please patch the > > PMIC-less boards in the following way: > > > #include "ipq6018.dtsi" > > &cpu_opp_table { > > /* the board doesn't have a PMIC, disable CPU frequencies which > > require higher voltages */ > > /delete-node/ opp-1320000000; > > /delete-node/ opp-1440000000; > >}; > > Thank you but no need. The CPUFreq NVMEM driver will give the CPU > maximum frequency based on the cpu_speed_bin and opp-supported-hw. From your patches I had the feeling that you still want to limit the high-frequency OPP entries if there is no PMIC. > > Thanks, > Chukun > > -- > 2.25.1 >
Hi, Dmitry > Straight to the board files, please, no need for additional includes. Is it possible to move the mp5496 node to mp5496.dtsi? Because ipq9574 also uses this mp5496 pmic. &rpm_requests { regulators { compatible = "qcom,rpm-mp5496-regulators"; mp5496_s1: s1 { regulator-min-microvolt = <725000>; regulator-max-microvolt = <1075000>; status = "disabled"; }; mp5496_s2: s2 { regulator-min-microvolt = <725000>; regulator-max-microvolt = <1062500>; status = "disabled"; }; mp5496_l2: l2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; status = "disabled"; }; }; }; > From your patches I had the feeling that you still want to limit the > high-frequency OPP entries if there is no PMIC. Sorry for this misunderstanding, the cpu max frequency is determined by the cpu_speed_bin. It's just that the efuse of the board I have without pmic are all 1.2GHz. Thanks, Chukun
On Thu, 1 Feb 2024 at 06:00, Chukun Pan <amadeus@jmu.edu.cn> wrote: > > Hi, Dmitry > > Straight to the board files, please, no need for additional includes. > > Is it possible to move the mp5496 node to mp5496.dtsi? > Because ipq9574 also uses this mp5496 pmic. > > &rpm_requests { > regulators { > compatible = "qcom,rpm-mp5496-regulators"; > > mp5496_s1: s1 { > regulator-min-microvolt = <725000>; > regulator-max-microvolt = <1075000>; > status = "disabled"; > }; > > mp5496_s2: s2 { > regulator-min-microvolt = <725000>; > regulator-max-microvolt = <1062500>; > status = "disabled"; > }; > > mp5496_l2: l2 { > regulator-min-microvolt = <1800000>; > regulator-max-microvolt = <3300000>; > status = "disabled"; > }; > }; > }; Usually this is a bad idea, the regulator boundaries are board specific. > > > From your patches I had the feeling that you still want to limit the > > high-frequency OPP entries if there is no PMIC. > > Sorry for this misunderstanding, the cpu max frequency is determined > by the cpu_speed_bin. It's just that the efuse of the board I have > without pmic are all 1.2GHz. Ack, sounds good then.
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index f5f4827c0e17..06dfc2cb6b7f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "ipq6018.dtsi" +#include "ipq6018-opp.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi new file mode 100644 index 000000000000..9c0bed2d8bf5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * IPQ60xx with PMIC (MP5496) CPU OPP tables + */ + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&cpu_speed_bin>; + opp-shared; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <725000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <787500>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <862500>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-microvolt = <925000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <987500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1062500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; +}; + +&CPU0 { + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; +}; + +&CPU1 { + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; +}; + +&CPU2 { + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; +}; + +&CPU3 { + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 5e1277fea725..ea72fd5739ac 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -41,8 +41,6 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; }; CPU1: cpu@1 { @@ -53,8 +51,6 @@ CPU1: cpu@1 { next-level-cache = <&L2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; }; CPU2: cpu@2 { @@ -65,8 +61,6 @@ CPU2: cpu@2 { next-level-cache = <&L2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; }; CPU3: cpu@3 { @@ -77,8 +71,6 @@ CPU3: cpu@3 { next-level-cache = <&L2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; }; L2_0: l2-cache { @@ -95,54 +87,6 @@ scm { }; }; - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2-kryo-cpu"; - nvmem-cells = <&cpu_speed_bin>; - opp-shared; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <725000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <787500>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <862500>; - opp-supported-hw = <0x3>; - clock-latency-ns = <200000>; - }; - - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-microvolt = <925000>; - opp-supported-hw = <0x3>; - clock-latency-ns = <200000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <987500>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1062500>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - }; - pmuv8: pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
Some IPQ6000 SoCs do not come with PMIC (MP5496) chip, which causes cpufreq to be unavailable due to lack of cpu-supply. Separate CPU OPP tables from soc.dtsi to support versions with and without PMIC chip. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 + arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi | 74 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 56 --------------- 3 files changed, 75 insertions(+), 56 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi