| Message ID | 20240209-qcm6490-gcc-protected-clocks-v2-1-11cd5fc13bd0@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 7c6bef576a8891abce08d448165b53328032aa5f |
| Headers | show |
| Series | [v2] arm64: dts: qcom: qcs6490-rb3gen2: Declare GCC clocks protected | expand |
On Sat, 10 Feb 2024 at 01:21, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > The SC7280 GCC binding describes clocks which, due to the difference in > security model, are not accessible on the RB3gen2 - in the same way seen > on QCM6490. > > Mark these clocks as protected, to allow the board to boot. In contrast > to the present QCM6490 boards GCC_EDP_CLKREF_EN is left out, as this > does not need to be "protected" and is used on the RB3Gen2 board. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > I did notice Taniya's patch [1] after writing this patch. I'd prefer to > merge this minimal set asap, to make the board boot, unless there's a > strong argument for including those other clocks in the protected list. > > [1] https://lore.kernel.org/linux-arm-msm/20240208062836.19767-6-quic_tdas@quicinc.com/ > --- > Changes in v2: > - Dropped GCC_EDP_CLKREF_EN from the list and expanded the commit > message to cover this descrepancy from QCM6490 devices. > - Corrected SC7180 to SC7280 in commit message. > - Link to v1: https://lore.kernel.org/r/20240209-qcm6490-gcc-protected-clocks-v1-1-bd3487b2e7b1@quicinc.com > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 8bb7d13d85f6..ebbe2c1123f6 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -413,6 +413,23 @@ vreg_bob_3p296: bob { > }; > }; > > +&gcc { > + protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, > + <GCC_MSS_CFG_AHB_CLK>, > + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, > + <GCC_MSS_OFFLINE_AXI_CLK>, > + <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, > + <GCC_MSS_SNOC_AXI_CLK>, > + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, > + <GCC_QSPI_CORE_CLK>, > + <GCC_QSPI_CORE_CLK_SRC>, > + <GCC_SEC_CTRL_CLK_SRC>, > + <GCC_WPSS_AHB_BDG_MST_CLK>, > + <GCC_WPSS_AHB_CLK>, > + <GCC_WPSS_RSCP_CLK>; > +}; Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Nit: I really suppose that parts like this should go to the common qcm6490.dtsi file, if it gets duplicated between IDP and RB3g2 boards. > + > &qupv3_id_0 { > status = "okay"; > }; > > --- > base-commit: b1d3a0e70c3881d2f8cf6692ccf7c2a4fb2d030d > change-id: 20240209-qcm6490-gcc-protected-clocks-ee5fafdb76b3 > > Best regards, > -- > Bjorn Andersson <quic_bjorande@quicinc.com> >
On Fri, 09 Feb 2024 15:21:48 -0800, Bjorn Andersson wrote: > The SC7280 GCC binding describes clocks which, due to the difference in > security model, are not accessible on the RB3gen2 - in the same way seen > on QCM6490. > > Mark these clocks as protected, to allow the board to boot. In contrast > to the present QCM6490 boards GCC_EDP_CLKREF_EN is left out, as this > does not need to be "protected" and is used on the RB3Gen2 board. > > [...] Applied, thanks! [1/1] arm64: dts: qcom: qcs6490-rb3gen2: Declare GCC clocks protected commit: 7c6bef576a8891abce08d448165b53328032aa5f Best regards,
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 8bb7d13d85f6..ebbe2c1123f6 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -413,6 +413,23 @@ vreg_bob_3p296: bob { }; }; +&gcc { + protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, + <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, + <GCC_MSS_OFFLINE_AXI_CLK>, + <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <GCC_MSS_SNOC_AXI_CLK>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_SEC_CTRL_CLK_SRC>, + <GCC_WPSS_AHB_BDG_MST_CLK>, + <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_RSCP_CLK>; +}; + &qupv3_id_0 { status = "okay"; };