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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id se14-20020a17090b518e00b00296d3598f9asm2910769pjb.35.2024.02.09.23.09.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:49 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org Subject: [PATCH 06/22] drm/bridge: Verify lane assignment is going to work during atomic_check Date: Fri, 9 Feb 2024 23:09:17 -0800 Message-ID: <20240210070934.2549994-7-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Verify during drm_atomic_bridge_check() that the lane assignment set in a bridge's atomic_check() callback is going to be satisfied by the previous bridge. If the next bridge is requiring something besides the default 1:1 lane assignment on its input then there must be an output lane assignment on the previous bridge's output. Otherwise the next bridge won't get the lanes assigned that it needs. Cc: Andrzej Hajda Cc: Neil Armstrong Cc: Robert Foss Cc: Laurent Pinchart Cc: Jonas Karlman Cc: Jernej Skrabec Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Daniel Vetter Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/gpu/drm/drm_bridge.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index 3fce0d8d7dcb..5097e7c65ddf 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -881,6 +881,10 @@ static int drm_atomic_bridge_check(struct drm_bridge *bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + u8 num_input_lanes, num_output_lanes = 0; + const struct drm_lane_cfg *input_lanes; + int i; + if (bridge->funcs->atomic_check) { struct drm_bridge_state *bridge_state; int ret; @@ -894,12 +898,24 @@ static int drm_atomic_bridge_check(struct drm_bridge *bridge, crtc_state, conn_state); if (ret) return ret; + num_output_lanes = bridge_state->output_bus_cfg.num_lanes; } else if (bridge->funcs->mode_fixup) { if (!bridge->funcs->mode_fixup(bridge, &crtc_state->mode, &crtc_state->adjusted_mode)) return -EINVAL; } + input_lanes = drm_bridge_next_bridge_lane_cfg(bridge, + crtc_state->state, + &num_input_lanes); + /* + * Ensure this bridge is aware that the next bridge wants to + * reassign lanes. + */ + for (i = 0; i < num_input_lanes; i++) + if (i != input_lanes[i].logical && !num_output_lanes) + return -ENOTSUPP; + return 0; }