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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id n7-20020a170906118700b00a3845a75eb7sm336246eja.189.2024.02.12.08.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 08:10:53 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 17:10:46 +0100 Subject: [PATCH v7 1/2] clk: qcom: branch: Add a helper for setting the enable bit Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-topic-clk_branch_en-v7-1-5b79eb7278b2@linaro.org> References: <20240212-topic-clk_branch_en-v7-0-5b79eb7278b2@linaro.org> In-Reply-To: <20240212-topic-clk_branch_en-v7-0-5b79eb7278b2@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Johan Hovold , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707754250; l=1404; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=b0wLfJlVaSUQG2JbwKmhWZbUkd5VW0gCuAeGx3m+/KQ=; b=YG/7NUziS4cLbLZKnjfCVh8PWY/engmAeD3WJiKsrfxEzniHJSiOOGADP/Y3eqGkv617/SxTg We79mvHoTu8A++0SMGZ4fzoUYqJVrIMGF60yra386fXl6eA41DbaUp7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= We hardcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Reviewed-by: Johan Hovold Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-branch.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 8ffed603c050..f1b3b635ff32 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -64,6 +64,7 @@ struct clk_mem_branch { #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) #define CBCR_WAKEUP GENMASK(11, 8) #define CBCR_SLEEP GENMASK(7, 4) +#define CBCR_CLOCK_ENABLE BIT(0) static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, struct clk_branch clk, bool on) @@ -98,6 +99,11 @@ static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branc FIELD_PREP(CBCR_SLEEP, val)); } +static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) +{ + regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, CBCR_CLOCK_ENABLE); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops;