From patchwork Tue Feb 20 13:51:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13564030 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF763745DE; Tue, 20 Feb 2024 13:53:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708437227; cv=none; b=JFeEb9bc6HlTPKpuhqtS9zrEW+CNuOudFwKfZ+6PwEvMKxf4lJS6Pc3xXWrUkFjL3GQ5HLwbeP7JGqtkDaxHyrcPw3VJvcafyRdZqKxlVwQfLSoUL0fB78PJjy4iJRbh9frKvk8Y62r5ia4VvWn2ptrYvGqsC2HQeJJl5C5z6UY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708437227; c=relaxed/simple; bh=8XWEOdKapLVhgNj0OiRoNdThFfoU0WXVrCU4na+Fs90=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iOY08vz+aZnUcO1RjLyk5h9ZhtICZ7prFdJYwxCheWcLeHD7jjMl1zIgq2/LuCIuui1NDd9oNZ4mMkfStJSWQ6kn5CjV+dK6RGFp4UuFGgJYlntGH7KT3zsWD7oOqjC7yIzRGbnkSqh0GElj9y+eyZLyx9csuzhxWhf/Y5GqjTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=TRX/qNwj; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="TRX/qNwj" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41KACT9J028655; Tue, 20 Feb 2024 13:53:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=+xUakRsrt3VKBLKGbRWgnEX+vZzasojdWPK4rBoSEO8=; b=TR X/qNwjyjnD/i09etd1nWjTS577cKfMt0ob99j8Aynvzit17SmPuTFQItJWC6iLii frJGjMD42UMECbJZDvNGlBe7MKRaQ9B48YRhc3wEbybh6b2W9+oh9r9mE4DR0Q1U aOYR4WB8Xz/OsMThjVbUVQ86CPfi92SPPHgH1SGf4+oZHwulh3cgeLMx6jdo5KX9 kgex2yvpeZJfq0xA08TWOKczwCOa1Jz8+mhp399Zw25ToLSHh1lIrPvMbhY+4wTR VzlNIg1J8Ltkqfx+dyNg+CoijYuLMvLoM47fXf+iV/dLZW/CoijFEgGJ7jQqfxZ9 zlrUlwDKg1S84SWDi1cw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wct3d0d7f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Feb 2024 13:53:41 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41KDrCNu005036 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Feb 2024 13:53:12 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 20 Feb 2024 05:53:07 -0800 From: Jagadeesh Kona To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Vladimir Zapolskiy , Jagadeesh Kona , Taniya Das , , , , , Ajit Pandey , Imran Shaik , "Satya Priya Kakitapalli" Subject: [PATCH V2 2/6] clk: qcom: videocc-sm8550: Add support for videocc XO clk ares Date: Tue, 20 Feb 2024 19:21:17 +0530 Message-ID: <20240220135121.22578-3-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240220135121.22578-1-quic_jkona@quicinc.com> References: <20240220135121.22578-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: IZjPh_AEN4P3-UTpN6JsbYu3nvggOEof X-Proofpoint-GUID: IZjPh_AEN4P3-UTpN6JsbYu3nvggOEof X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402200100 Add support for videocc XO clk ares for consumer drivers to be able to request for this reset. Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/videocc-sm8550.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index d73f747d2474..3a19204a9063 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, }; static const struct regmap_config video_cc_sm8550_regmap_config = {