From patchwork Thu Feb 22 19:40:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paloma Arellano X-Patchwork-Id: 13568018 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71A506AFB7 for ; Thu, 22 Feb 2024 19:41:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708630863; cv=none; b=UnAOTUuLeTajEZNB4/rR8IqxR+TSBdX9nZwCmwkslQp1xNDNpV7bmeFvWOSsxlsUpK+nvFrsX1xS4s+4Cpx/0N3H0rebQGkuvEGaAShDIyxEopVZUK3nSToRPlpPkf3oioJ2xEAQQlHbF88Wm+e/DqDdi4Xygl28RKI+0k4jvY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708630863; c=relaxed/simple; bh=MlRamHdR0Y3NFOcS+bG5xi77MZ6zyCNbEs7tsaPl9Js=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MXtjr72NNHdJdzNfZJ+20dF6k9zQSrj10pN3TdmeCWruMAeZLCKUlUld6HoccHfKAIZP7kQwX91xehhEnPv2GEDh77IvweEPtAUkw7724ItN3x1k50AjE+EgfoLSw3DfAfZLoRB06YpIsGsMvAg/xsuWcZju8F8kvb9Oz3Dvk5c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=LTByYPlR; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="LTByYPlR" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41MHXcPa011331; Thu, 22 Feb 2024 19:40:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=5zapvQt+14Sv0pTOUa7H2a+Zz4/4jISDQVvGnMb1gPY=; b=LT ByYPlR/uA4oJ7iE69a4vVmE248MZtLtu1KGXhBzAws9nEIiomlL8WVKdAfWwlkba hTjS3NJbhVC8Rtq/dTSti0A1oTBDP0dNpv1R7v3f1tKQ4QOvFtYjyZqeSQk/MKWi RytJoAPBWlNc9W2xT1OoQ7TbdQpA0ciY08cEcKg6XX3//M37LQfPOmWCumXJ+4AE +Ye9PYSTCDdsQEAi5S48dPWIKe4Y0eiLsZi9QrqN+NmtwfqHTyoGYmqaZeDDR0+Q EuW6+GyIp8smRbhqj1Xy7/oXWmq9rtK8UnuI4mJxCmdDDMKBXTsZO+RngR8khpZc TwVidj22oSaWHRY6n/Wg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3weasbrkt2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Feb 2024 19:40:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41MJeu5E022787 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Feb 2024 19:40:56 GMT Received: from hu-parellan-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 22 Feb 2024 11:40:55 -0800 From: Paloma Arellano To: CC: Paloma Arellano , , , , , , , , , , , Subject: [PATCH v5 18/19] drm/msm/dpu: reserve CDM blocks for DP if mode is YUV420 Date: Thu, 22 Feb 2024 11:40:03 -0800 Message-ID: <20240222194025.25329-19-quic_parellan@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240222194025.25329-1-quic_parellan@quicinc.com> References: <20240222194025.25329-1-quic_parellan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: X_XIqUmqKqPUOGECX5W7WEPUn7AI6y2H X-Proofpoint-GUID: X_XIqUmqKqPUOGECX5W7WEPUn7AI6y2H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_15,2024-02-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 phishscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402220154 Reserve CDM blocks for DP if the mode format is YUV420. Currently this reservation only works for writeback and DP if the format is YUV420. But this can be easily extented to other YUV formats for DP. Changes in v2: - Minor code simplification Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 22 +++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 84778adc7f791..e636215c8f834 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -635,6 +635,7 @@ static int dpu_encoder_virt_atomic_check( struct dpu_kms *dpu_kms; struct drm_display_mode *adj_mode; struct msm_display_topology topology; + struct msm_display_info *disp_info; struct dpu_global_state *global_state; struct drm_framebuffer *fb; struct drm_dsc_config *dsc; @@ -651,6 +652,7 @@ static int dpu_encoder_virt_atomic_check( DPU_DEBUG_ENC(dpu_enc, "\n"); priv = drm_enc->dev->dev_private; + disp_info = &dpu_enc->disp_info; dpu_kms = to_dpu_kms(priv->kms); adj_mode = &crtc_state->adjusted_mode; global_state = dpu_kms_get_global_state(crtc_state->state); @@ -678,21 +680,24 @@ static int dpu_encoder_virt_atomic_check( topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); /* - * Use CDM only for writeback at the moment as other interfaces cannot handle it. - * if writeback itself cannot handle cdm for some reason it will fail in its atomic_check() + * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. + * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check() * earlier. */ - if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { + if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { fb = conn_state->writeback_job->fb; if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb)))) topology.needs_cdm = true; - if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm) - crtc_state->mode_changed = true; - else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm) - crtc_state->mode_changed = true; + } else if (disp_info->intf_type == INTF_DP) { + if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode)) + topology.needs_cdm = true; } + if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm) + crtc_state->mode_changed = true; + else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm) + crtc_state->mode_changed = true; /* * Release and Allocate resources on every modeset * Dont allocate when active is false. @@ -1133,7 +1138,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, dpu_enc->dsc_mask = dsc_mask; - if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { + if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) || + dpu_enc->disp_info.intf_type == INTF_DP) { struct dpu_hw_blk *hw_cdm = NULL; dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,