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Fri, 23 Feb 2024 14:48:46 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 23 Feb 2024 06:48:39 -0800 From: Krishna chaitanya chundru Date: Fri, 23 Feb 2024 20:18:01 +0530 Subject: [PATCH v7 4/7] dt-bindings: pci: qcom: Add opp table Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240223-opp_support-v7-4-10b4363d7e71@quicinc.com> References: <20240223-opp_support-v7-0-10b4363d7e71@quicinc.com> In-Reply-To: <20240223-opp_support-v7-0-10b4363d7e71@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Rob Herring , Johan Hovold , Brian Masney , Georgi Djakov CC: , , , , , , , , , Krishna chaitanya chundru , Krzysztof Kozlowski X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Adding the Operating Performance Points table allows to adjust power domain performance state and icc peak bw, depending on the PCIe gen speed and width. Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 5ad5c4cfd2a8..e1d75cabb1a9 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -127,6 +127,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - compatible - reg