From patchwork Mon Feb 26 17:22:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 13572548 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DE1B130E53; Mon, 26 Feb 2024 17:22:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708968178; cv=none; b=FrZ1bSK4jytvqwIDvsh9XG5A2qMG3D2QiCfrEKdGnCXH10x8+cIeKO41gLuEUbRTiVxEogR/DgwLmGJOlM2x1/0b1Ln/i4gNFegN2gIDgGDGvtXY33dply4MEf4nQigQ+BpD6r9dTgtCoJTCeKSUMXvGNMpNapBkjtlAlnJ69k8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708968178; c=relaxed/simple; bh=QwUtbYnK0FdBx8nUUx/hg1vm3Ycb0gWRaFhynPbO3yc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VQ5JIugTcYmoShMg1hhS4YveVs6KE8uY1cNnXyAliraeSf/BlQTBIK2h/oSLKz7KomQ5zLHB0xD1TyPruSA7nB0opR5FeAhYoNv8HFWzvx1znKyqdxJl+QNXai/EYY0KeO/UQMdB8wWOeNQe3vVwKFg8RPgeGaCJeLWqP/mLRRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Pxp6utyd; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Pxp6utyd" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41QGnUvr026490; Mon, 26 Feb 2024 17:22:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=kYZJ3XFYhLBbl9IjdTWgLrDUVbqUM6Hq5QENP4sv9us=; b=Px p6utydjYEqQO/Y9xkAbpOOAV4FxtZwpcODS8x8YnpNcMSrLbDq7SScAaT5a9FUXd 7/aK6CdEhEmqhQPuTgH3oD2Fz0waBiu75qUI4oJw9CiLUwni2JUaoPmGlYbYuwAw xIRH4dlDKQ1BR94EOc9v1+2iAL5TqKdgpxqJVwroGLoKm5HanlU4fu3JuRYqlV+J ZrlzIU9iMbk2HnXtB6C9I0c5PwYVzadKs5NlVUZvk3+c3JSid5JDANLSj98syiDE 0VxQCYv8IdQhE1+GZDjE3M6kK7u4eIstwPX2cPomrUfXI7vK1puSj1prwO44/wLc PXFV5tfJLnBsj2Wr1lNg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wgkxn9j6g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 26 Feb 2024 17:22:37 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41QHMaEx019973 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 26 Feb 2024 17:22:36 GMT Received: from hu-c-gdjako-lv.qualcomm.com (10.49.16.6) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 26 Feb 2024 09:22:35 -0800 From: Georgi Djakov To: , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v5 6/7] iommu/arm-smmu-qcom: Use the custom fault handler on more platforms Date: Mon, 26 Feb 2024 09:22:17 -0800 Message-ID: <20240226172218.69486-7-quic_c_gdjako@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240226172218.69486-1-quic_c_gdjako@quicinc.com> References: <20240226172218.69486-1-quic_c_gdjako@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0ebkddyVG0Iz2kH9GWCZXx1KtoNJ816S X-Proofpoint-GUID: 0ebkddyVG0Iz2kH9GWCZXx1KtoNJ816S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_11,2024-02-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 impostorscore=0 clxscore=1015 malwarescore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402260132 The TBU support is now available, so let's allow it to be used on other platforms that have the Qualcomm SMMU-500 implementation with TBUs. This will allow the context fault handler to query the TBUs when a context fault occurs. Signed-off-by: Georgi Djakov --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index a8238f75c5d3..929f1d205526 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -412,6 +412,10 @@ static const struct arm_smmu_impl qcom_smmu_500_impl = { .reset = arm_mmu500_reset, .write_s2cr = qcom_smmu_write_s2cr, .tlb_sync = qcom_smmu_tlb_sync, +#ifdef CONFIG_ARM_SMMU_QCOM_TBU + .context_fault = qcom_smmu_context_fault, + .context_fault_needs_threaded_irq = true, +#endif }; static const struct arm_smmu_impl sdm845_smmu_500_impl = {