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a=openpgp-sha256; l=2908; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=hHeQESdb2n2JfoPbQGhczuNq7aes0p4VCwzYiQEpxZY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl8xaQfg97viBuOIgmUL62KebaBZQIQNgdeCdUj aCgxk36waWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfMWkAAKCRBVnxHm/pHO 9dH/B/93GdKJANpOSa22x4XiYazPXmYMSF7FXM0F0/rb0MhOjtc62toq2EEl6mi3yPtj3T/Gz5j ea1MwxgLD8daifKkQZmj1ZyR6luJ4Xar+fQFq3jcSvB+S2TDdgPmHA/dMtCYUBnO415ZZlEgxyi kn5bs1s2wkckx37TU65QJHX+Hffu/kuodZSw+zYUvnLwSEfkbw4xXUjuySbTnVVoR1pa6TuQT4M eLFMtcYj4maR+1bcv7bSGm9KXeJWHl3j7igzlknj4moBwRwE4UBQlVAxbhSIlsh9ObXdfhE12c0 tZAkWrM06kPRlEbBYazKyTQ6wbkB+Vfid8ikgvuzgVrcUsdR X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 DWC specific start_link() and stop_link() callbacks are supposed to start and stop the link training of the PCIe bus. But the current implementation of this driver enables/disables the PERST# IRQ. Even though this is not causing any issues, this creates inconsistency among the controller drivers. So for the sake of consistency, let's just start/stop the link training in these callbacks. Also, PERST# IRQ is now enabled from the start itself, thus allowing the controller driver to initialize the registers when PERST# gets deasserted without waiting for the user intervention though configfs. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 811f250e967a..653e4ace0a07 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -122,6 +122,9 @@ /* PARF_CFG_BITS register fields */ #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) +/* PARF_LTSSM register fields */ +#define LTSSM_EN BIT(8) + /* ELBI registers */ #define ELBI_SYS_STTS 0x08 #define ELBI_CS2_ENABLE 0xa4 @@ -250,8 +253,12 @@ static int qcom_pcie_dw_link_up(struct dw_pcie *pci) static int qcom_pcie_dw_start_link(struct dw_pcie *pci) { struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + u32 val; - enable_irq(pcie_ep->perst_irq); + /* Enable LTSSM */ + val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); + val |= LTSSM_EN; + writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); return 0; } @@ -259,8 +266,12 @@ static int qcom_pcie_dw_start_link(struct dw_pcie *pci) static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) { struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + u32 val; - disable_irq(pcie_ep->perst_irq); + /* Disable LTSSM */ + val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); + val &= ~LTSSM_EN; + writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); } static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, @@ -484,11 +495,6 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) dw_pcie_ep_init_notify(&pcie_ep->pci.ep); - /* Enable LTSSM */ - val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); - val |= BIT(8); - writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); - return 0; err_disable_resources: @@ -707,7 +713,6 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, } pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); - irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, qcom_pcie_ep_perst_irq_thread, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,