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Thu, 21 Mar 2024 04:17:16 -0700 (PDT) Received: from [127.0.1.1] ([2409:40f4:102b:a64b:d832:a82a:837c:6d3]) by smtp.gmail.com with ESMTPSA id ka6-20020a056a00938600b006e7324d32bbsm5531120pfb.122.2024.03.21.04.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 04:17:15 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:29 +0530 Subject: [PATCH v2 09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-pcie-qcom-bridge-dts-v2-9-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3370; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=xm+jWg3BgMqQCkkC5ZHr8tW7UJ1z5Sx/tGZleR1ATvE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl/BcL1+Vnkfwh+YBo40ZqpcGU2fjgvQ30/12dm asb8ZOvofKJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfwXCwAKCRBVnxHm/pHO 9TY1B/9WeLAXW+OaaT824XlTb276fkWKMEenfw0+X+0fmDRWIkEq8FN3zl2VsT4L0pc/Z+F4jPY HwNobpUhR20Vd/QsgCjO2LEMgosGWAQ3mNkraRpH64xuxh+a+EL8+GilybSRWRlds9nYBqQ4pH8 kVMAe3ozmVc8g8B/bcusILRnPMcjkQche0EV3EBlwLOaV/Z+NmZO+P3w9boTyaZl9xzrLY/s1QV M+VRQpWGdXCj/fc11xeVhPOhqVA6Rec6Ay8aU0QtUD1ImCof8C7t1Mmz2+7JnTfqJxpF627+/Z6 jxzUGCkZukPcEi+bI83OomX+XP49wxM9qD75hWNmBAE/nqoM X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. While at it, let's remove the bridge properties from board dts as they are now redundant. Signed-off-by: Manivannan Sadhasivam --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 +++------ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 50 ++++++++++++++++++++++ 2 files changed, 56 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 15ae94c1602d..caf7dff446a6 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -731,22 +731,14 @@ &pcie4 { pinctrl-0 = <&pcie4_default>; status = "okay"; +}; - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - bus-range = <0x01 0xff>; - - wifi@0 { - compatible = "pci17cb,1103"; - reg = <0x10000 0x0 0x0 0x0 0x0>; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; - qcom,ath11k-calibration-variant = "LE_X13S"; - }; + qcom,ath11k-calibration-variant = "LE_X13S"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a5b194813079..c7feebcb28b9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1779,6 +1779,16 @@ pcie4: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie4_phy: phy@1c06000 { @@ -1877,6 +1887,16 @@ pcie3b: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie3b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3b_phy: phy@1c0e000 { @@ -1975,6 +1995,16 @@ pcie3a: pcie@1c10000 { phy-names = "pciephy"; status = "disabled"; + + pcie3a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3a_phy: phy@1c14000 { @@ -2076,6 +2106,16 @@ pcie2b: pcie@1c18000 { phy-names = "pciephy"; status = "disabled"; + + pcie2b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2b_phy: phy@1c1e000 { @@ -2174,6 +2214,16 @@ pcie2a: pcie@1c20000 { phy-names = "pciephy"; status = "disabled"; + + pcie2a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2a_phy: phy@1c24000 {