Message ID | 20240325102036.95484-2-quic_varada@quicinc.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show
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Mon, 25 Mar 2024 10:21:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42PAL17x030979 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 10:21:01 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 25 Mar 2024 03:20:56 -0700 From: Varadarajan Narayanan <quic_varada@quicinc.com> To: <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <djakov@kernel.org>, <quic_anusha@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org> CC: Varadarajan Narayanan <quic_varada@quicinc.com> Subject: [PATCH v2 1/4] dt-bindings: clock: Add interconnect-cells Date: Mon, 25 Mar 2024 15:50:33 +0530 Message-ID: <20240325102036.95484-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240325102036.95484-1-quic_varada@quicinc.com> References: <20240325102036.95484-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 7EhsKU-ofCHWDine0EAnAjN4uZOT8TRs X-Proofpoint-GUID: 7EhsKU-ofCHWDine0EAnAjN4uZOT8TRs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-25_07,2024-03-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403250056 |
Series | Add interconnect driver for IPQ9574 SoC | expand |
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6..824781cbdf34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,9 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#interconnect-cells': + const: 1 + required: - compatible - clocks
Add interconnect-cells to clock provider so that it can be used as icc provider Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml | 3 +++ 1 file changed, 3 insertions(+)