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Tue, 16 Apr 2024 11:03:18 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 43GB3HXb023062; Tue, 16 Apr 2024 11:03:17 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-vdadhani-hyd.qualcomm.com [10.213.106.28]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 43GB3AiR023031; Tue, 16 Apr 2024 11:03:17 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 4047106) id 6873C500C6C; Tue, 16 Apr 2024 16:26:52 +0530 (+0530) From: Viken Dadhaniya To: cros-qcom-dts-watchers@chromium.org, andersson@kernel.org, konrad.dybcio@linaro.org, swboyd@chromium.org, robh@kernel.org, krzk+dt@kernel.org, linux-arm-msm@vger.kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rajpat@codeaurora.org, mka@chromium.org, rojay@codeaurora.org Cc: quic_msavaliy@quicinc.com, quic_anupkulk@quicinc.com, Viken Dadhaniya Subject: [PATCH v1] arm64: dts: qcom: sc7280: Remove CTS/RTS configuration Date: Tue, 16 Apr 2024 16:26:50 +0530 Message-Id: <20240416105650.2626-1-quic_vdadhani@quicinc.com> X-Mailer: git-send-email 2.17.1 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7w5elmBqewWqENvqVGj37HW3b70ZecdR X-Proofpoint-ORIG-GUID: 7w5elmBqewWqENvqVGj37HW3b70ZecdR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-16_08,2024-04-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 adultscore=0 mlxscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=956 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404160068 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Remove CTS and RTS pinctrl configuration for UART5 node as it's designed for debug UART for all the board variants of the sc7280 chipset. Also change compatible string to debug UART. Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") Signed-off-by: Viken Dadhaniya --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 38c183b2bb26..2a6b4c4639d1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1440,12 +1440,12 @@ }; uart5: serial@994000 { - compatible = "qcom,geni-uart"; + compatible = "qcom,geni-debug-uart"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; @@ -5397,16 +5397,6 @@ function = "qup04"; }; - qup_uart5_cts: qup-uart5-cts-state { - pins = "gpio20"; - function = "qup05"; - }; - - qup_uart5_rts: qup-uart5-rts-state { - pins = "gpio21"; - function = "qup05"; - }; - qup_uart5_tx: qup-uart5-tx-state { pins = "gpio22"; function = "qup05";