| Message ID | 20240420044901.884098-10-quic_kriskura@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Add multiport support for DWC3 controllers | expand |
On Sat, Apr 20, 2024 at 10:19:01AM +0530, Krishna Kurapati wrote: > Power event IRQ is used for wakeup either when the controller is > SuperSpeed capable but is missing an SuperSpeed PHY interrupt, or when > the GIC is not capable of detecting DP/DM High-Speed PHY interrupts. > > The Power event IRQ stat register indicates whether the High-Speed > phy entered and exited L2 successfully during suspend and resume. > Indicate the same for all ports of a multiport controller. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
On Sat, Apr 20, 2024, Krishna Kurapati wrote: > Power event IRQ is used for wakeup either when the controller is > SuperSpeed capable but is missing an SuperSpeed PHY interrupt, or when > the GIC is not capable of detecting DP/DM High-Speed PHY interrupts. > > The Power event IRQ stat register indicates whether the High-Speed > phy entered and exited L2 successfully during suspend and resume. > Indicate the same for all ports of a multiport controller. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > drivers/usb/dwc3/dwc3-qcom.c | 23 +++++++++++++++++------ > 1 file changed, 17 insertions(+), 6 deletions(-) > > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c > index b6f13bb14e2c..88fb6706a18d 100644 > --- a/drivers/usb/dwc3/dwc3-qcom.c > +++ b/drivers/usb/dwc3/dwc3-qcom.c > @@ -36,7 +36,6 @@ > #define PIPE3_PHYSTATUS_SW BIT(3) > #define PIPE_UTMI_CLK_DIS BIT(8) > > -#define PWR_EVNT_IRQ_STAT_REG 0x58 > #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) > #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) > > @@ -55,6 +54,13 @@ > /* Qualcomm SoCs with multiport support has up to 4 ports */ > #define DWC3_QCOM_MAX_PORTS 4 > > +static const u32 pwr_evnt_irq_stat_reg[DWC3_QCOM_MAX_PORTS] = { > + 0x58, > + 0x1dc, > + 0x228, > + 0x238, > +}; > + > struct dwc3_qcom_port { > int qusb2_phy_irq; > int dp_hs_phy_irq; > @@ -424,9 +430,11 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) > if (qcom->is_suspended) > return 0; > > - val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); > - if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) > - dev_err(qcom->dev, "HS-PHY not in L2\n"); > + for (i = 0; i < qcom->num_ports; i++) { > + val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]); > + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) > + dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1); > + } > > for (i = qcom->num_clocks - 1; i >= 0; i--) > clk_disable_unprepare(qcom->clks[i]); > @@ -475,8 +483,11 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) > dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); > > /* Clear existing events from PHY related to L2 in/out */ > - dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, > - PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); > + for (i = 0; i < qcom->num_ports; i++) { > + dwc3_qcom_setbits(qcom->qscratch_base, > + pwr_evnt_irq_stat_reg[i], > + PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); > + } > > qcom->is_suspended = false; > > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index b6f13bb14e2c..88fb6706a18d 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -36,7 +36,6 @@ #define PIPE3_PHYSTATUS_SW BIT(3) #define PIPE_UTMI_CLK_DIS BIT(8) -#define PWR_EVNT_IRQ_STAT_REG 0x58 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) @@ -55,6 +54,13 @@ /* Qualcomm SoCs with multiport support has up to 4 ports */ #define DWC3_QCOM_MAX_PORTS 4 +static const u32 pwr_evnt_irq_stat_reg[DWC3_QCOM_MAX_PORTS] = { + 0x58, + 0x1dc, + 0x228, + 0x238, +}; + struct dwc3_qcom_port { int qusb2_phy_irq; int dp_hs_phy_irq; @@ -424,9 +430,11 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) if (qcom->is_suspended) return 0; - val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); - if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) - dev_err(qcom->dev, "HS-PHY not in L2\n"); + for (i = 0; i < qcom->num_ports; i++) { + val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]); + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) + dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1); + } for (i = qcom->num_clocks - 1; i >= 0; i--) clk_disable_unprepare(qcom->clks[i]); @@ -475,8 +483,11 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); /* Clear existing events from PHY related to L2 in/out */ - dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, - PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); + for (i = 0; i < qcom->num_ports; i++) { + dwc3_qcom_setbits(qcom->qscratch_base, + pwr_evnt_irq_stat_reg[i], + PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); + } qcom->is_suspended = false;