diff mbox series

[v2] arm64: dts: qcom: sc7280: Remove CTS/RTS configuration

Message ID 20240424075853.11445-1-quic_vdadhani@quicinc.com (mailing list archive)
State Queued
Headers show
Series [v2] arm64: dts: qcom: sc7280: Remove CTS/RTS configuration | expand

Commit Message

Viken Dadhaniya April 24, 2024, 7:58 a.m. UTC
For IDP variant, GPIO 20/21 is used by camera use case and camera
driver is not able acquire these GPIOs as it is acquired by UART5
driver as RTS/CTS pin.

UART5 is designed for debug UART for all the board variants of the
sc7280 chipset and RTS/CTS configuration is not required for debug
uart usecase.

Remove CTS/RTS configuration for UART5 instance and change compatible
string to debug UART.

Remove overwriting compatible property from individual target specific
file as it is not required.

Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node")
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>

---
v1 -> v2:
- Remove compatible property from target specific file.
- Update commit log.
---
 arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts |  1 -
 arch/arm64/boot/dts/qcom/qcm6490-idp.dts           |  1 -
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts       |  1 -
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi           |  1 -
 arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi         |  1 -
 arch/arm64/boot/dts/qcom/sc7280.dtsi               | 14 ++------------
 6 files changed, 2 insertions(+), 17 deletions(-)

Comments

Rob Herring April 24, 2024, 1:14 p.m. UTC | #1
On Wed, 24 Apr 2024 13:28:53 +0530, Viken Dadhaniya wrote:
> For IDP variant, GPIO 20/21 is used by camera use case and camera
> driver is not able acquire these GPIOs as it is acquired by UART5
> driver as RTS/CTS pin.
> 
> UART5 is designed for debug UART for all the board variants of the
> sc7280 chipset and RTS/CTS configuration is not required for debug
> uart usecase.
> 
> Remove CTS/RTS configuration for UART5 instance and change compatible
> string to debug UART.
> 
> Remove overwriting compatible property from individual target specific
> file as it is not required.
> 
> Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node")
> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
> 
> ---
> v1 -> v2:
> - Remove compatible property from target specific file.
> - Update commit log.
> ---
>  arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts |  1 -
>  arch/arm64/boot/dts/qcom/qcm6490-idp.dts           |  1 -
>  arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts       |  1 -
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi           |  1 -
>  arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi         |  1 -
>  arch/arm64/boot/dts/qcom/sc7280.dtsi               | 14 ++------------
>  6 files changed, 2 insertions(+), 17 deletions(-)
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y qcom/qcm6490-fairphone-fp5.dtb qcom/qcm6490-idp.dtb qcom/qcs6490-rb3gen2.dtb' for 20240424075853.11445-1-quic_vdadhani@quicinc.com:

arch/arm64/boot/dts/qcom/qcm6490-idp.dtb: usb@8cf8800: interrupt-names: ['pwr_event', 'hs_phy_irq', 'dp_hs_phy_irq', 'dm_hs_phy_irq'] is too short
	from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
Bjorn Andersson May 27, 2024, 3 a.m. UTC | #2
On Wed, 24 Apr 2024 13:28:53 +0530, Viken Dadhaniya wrote:
> For IDP variant, GPIO 20/21 is used by camera use case and camera
> driver is not able acquire these GPIOs as it is acquired by UART5
> driver as RTS/CTS pin.
> 
> UART5 is designed for debug UART for all the board variants of the
> sc7280 chipset and RTS/CTS configuration is not required for debug
> uart usecase.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: qcom: sc7280: Remove CTS/RTS configuration
      commit: 2b96407b8f10f1d71b58cb35704eb91b8ea78db1

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
index f3432701945f..8cd2fe80dbb2 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
@@ -864,7 +864,6 @@ 
 };
 
 &uart5 {
-	compatible = "qcom,geni-debug-uart";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
index 47ca2d000341..107302680f56 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
@@ -658,7 +658,6 @@ 
 };
 
 &uart5 {
-	compatible = "qcom,geni-debug-uart";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index a085ff5b5fb2..7256b51eb08f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -632,7 +632,6 @@ 
 };
 
 &uart5 {
-	compatible = "qcom,geni-debug-uart";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index a0059527d9e4..7370aa0dbf0e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -495,7 +495,6 @@ 
 };
 
 &uart5 {
-	compatible = "qcom,geni-debug-uart";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
index f9b96bd2477e..7d1d5bbbbbd9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
@@ -427,7 +427,6 @@ 
 };
 
 uart_dbg: &uart5 {
-	compatible = "qcom,geni-debug-uart";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fc9ec367e3a5..246fb7919d27 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1440,12 +1440,12 @@ 
 			};
 
 			uart5: serial@994000 {
-				compatible = "qcom,geni-uart";
+				compatible = "qcom,geni-debug-uart";
 				reg = <0 0x00994000 0 0x4000>;
 				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 				clock-names = "se";
 				pinctrl-names = "default";
-				pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
+				pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
 				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&rpmhpd SC7280_CX>;
 				operating-points-v2 = <&qup_opp_table>;
@@ -5407,16 +5407,6 @@ 
 				function = "qup04";
 			};
 
-			qup_uart5_cts: qup-uart5-cts-state {
-				pins = "gpio20";
-				function = "qup05";
-			};
-
-			qup_uart5_rts: qup-uart5-rts-state {
-				pins = "gpio21";
-				function = "qup05";
-			};
-
 			qup_uart5_tx: qup-uart5-tx-state {
 				pins = "gpio22";
 				function = "qup05";