| Message ID | 20240531090249.10293-8-quic_tdas@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for SA8775P Multimedia clock controllers | expand |
On 31/05/2024 11:02, Taniya Das wrote: > Add device tree bindings for the video clock controller on Qualcomm > SA8775P platform. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > .../bindings/clock/qcom,sa8775p-videocc.yaml | 75 +++++++++++++++++++ > .../dt-bindings/clock/qcom,sa8775p-videocc.h | 47 ++++++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml > create mode 100644 include/dt-bindings/clock/qcom,sa8775p-videocc.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml > new file mode 100644 > index 000000000000..3edb29d0e5eb > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Video Clock & Reset Controller on SA8775P > + > +maintainers: > + - Taniya Das <quic_tdas@quicinc.com> > + > +description: | > + Qualcomm video clock control module provides the clocks, resets and power > + domains on SA8775P. > + > + See also:: include/dt-bindings/clock/qcom,sa8775p-videocc.h Just single ':' > + > +properties: > + compatible: > + enum: > + - qcom,sa8775p-videocc I am not sure if you are sure what you are doing... so to clarify: SA8775p is going significant bindings rework, so in general please post bindings matching new firmware (so SCMI consensus) or something which will be stable. Don't post something which tomorrow will need changes. Does this binding fits new style or is going to be considered stable? > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Video AHB clock from GCC > + - description: Board XO source > + - description: Board active XO source > + - description: Sleep Clock source > + > + power-domains: > + maxItems: 1 > + description: > + MMCX power domain. > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - power-domains > + - '#clock-cells' > + - '#reset-cells' > + - '#power-domain-cells' Drop redundant properties and reference qcom,gcc.yaml. > +#endif Best regards, Krzysztof
On 5/31/2024 7:29 PM, Krzysztof Kozlowski wrote: > On 31/05/2024 11:02, Taniya Das wrote: >> Add device tree bindings for the video clock controller on Qualcomm >> SA8775P platform. >> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> .../bindings/clock/qcom,sa8775p-videocc.yaml | 75 +++++++++++++++++++ >> .../dt-bindings/clock/qcom,sa8775p-videocc.h | 47 ++++++++++++ >> 2 files changed, 122 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml >> create mode 100644 include/dt-bindings/clock/qcom,sa8775p-videocc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml >> new file mode 100644 >> index 000000000000..3edb29d0e5eb >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml >> @@ -0,0 +1,75 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Video Clock & Reset Controller on SA8775P >> + >> +maintainers: >> + - Taniya Das <quic_tdas@quicinc.com> >> + >> +description: | >> + Qualcomm video clock control module provides the clocks, resets and power >> + domains on SA8775P. >> + >> + See also:: include/dt-bindings/clock/qcom,sa8775p-videocc.h > > Just single ':' > Will be fixed. >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,sa8775p-videocc > > I am not sure if you are sure what you are doing... so to clarify: > SA8775p is going significant bindings rework, so in general please post > bindings matching new firmware (so SCMI consensus) or something which > will be stable. > > Don't post something which tomorrow will need changes. > > Does this binding fits new style or is going to be considered stable? > Both these approaches should be supported for SA8775p. 1. SCMI to control the clock/NoC resources. 2. Clocks to be controlled via High Level OS(e.g. VideoCC driver). The expectation of the 1st approach is not to change/update any driver supported. Hope I am able to clarify. Please let me know if you have more queries on the same. >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Video AHB clock from GCC >> + - description: Board XO source >> + - description: Board active XO source >> + - description: Sleep Clock source >> + >> + power-domains: >> + maxItems: 1 >> + description: >> + MMCX power domain. >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#reset-cells': >> + const: 1 >> + >> + '#power-domain-cells': >> + const: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - power-domains >> + - '#clock-cells' >> + - '#reset-cells' >> + - '#power-domain-cells' > > Drop redundant properties and reference qcom,gcc.yaml. > I will update in the next series. >> +#endif > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml new file mode 100644 index 000000000000..3edb29d0e5eb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SA8775P + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SA8775P. + + See also:: include/dt-bindings/clock/qcom,sa8775p-videocc.h + +properties: + compatible: + enum: + - qcom,sa8775p-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Video AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep Clock source + + power-domains: + maxItems: 1 + description: + MMCX power domain. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + videocc: clock-controller@abf0000 { + compatible = "qcom,sa8775p-videocc"; + reg = <0x0abf0000 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-videocc.h b/include/dt-bindings/clock/qcom,sa8775p-videocc.h new file mode 100644 index 000000000000..e6325f68c317 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-videocc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H +#define _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0C_CLK 5 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6 +#define VIDEO_CC_MVS1_CLK 7 +#define VIDEO_CC_MVS1_CLK_SRC 8 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS1C_CLK 10 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 +#define VIDEO_CC_PLL_LOCK_MONITOR_CLK 12 +#define VIDEO_CC_SLEEP_CLK 13 +#define VIDEO_CC_SLEEP_CLK_SRC 14 +#define VIDEO_CC_SM_DIV_CLK_SRC 15 +#define VIDEO_CC_SM_OBS_CLK 16 +#define VIDEO_CC_XO_CLK 17 +#define VIDEO_CC_XO_CLK_SRC 18 +#define VIDEO_PLL0 19 +#define VIDEO_PLL1 20 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_MVS0C_BCR 3 +#define VIDEO_CC_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_BCR 6 + +#endif
Add device tree bindings for the video clock controller on Qualcomm SA8775P platform. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- .../bindings/clock/qcom,sa8775p-videocc.yaml | 75 +++++++++++++++++++ .../dt-bindings/clock/qcom,sa8775p-videocc.h | 47 ++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml create mode 100644 include/dt-bindings/clock/qcom,sa8775p-videocc.h