Message ID | 20240612124056.39230-4-quic_sibis@quicinc.com (mailing list archive) |
---|---|
State | Changes Requested |
Headers | show |
Series | qcom: x1e80100: Enable CPUFreq | expand |
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 9944c654851e..28ae10c24a5f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5091,7 +5091,7 @@ apps_smmu: iommu@15000000 { intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0 0x17000000 0 0x10000>, /* GICD */ - <0 0x17080000 0 0x480000>; /* GICR * 12 */ + <0 0x17080000 0 0x300000>; /* GICR * 12 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;