| Message ID | 20240618-starqltechn_integration_upstream-v3-2-e3f6662017ac@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | This is continued work on Samsung S9(SM-9600) starqltechn | expand |
On Tue, Jun 18, 2024 at 04:59:36PM GMT, Dzmitry Sankouski wrote: > sdm845 has "General Purpose" clocks that can be muxed to > SoC pins. > > Those clocks may be used as e.g. PWM sources for external peripherals. > Add more frequencies to the table for those clocks so it's possible > for arbitrary peripherals to make use of them. > > See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks) Each time I look at the table attached to the GP CLK, I feel that it's plain wrong. In the end the GPCLK can in theory have arbitrary value depending on the usecase. Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which allow more flexibility than a default clk_rcg2_ops? > > Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> > --- > drivers/clk/qcom/gcc-sdm845.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c > index ea4c3bf4fb9b..0efd3364e8f5 100644 > --- a/drivers/clk/qcom/gcc-sdm845.c > +++ b/drivers/clk/qcom/gcc-sdm845.c > @@ -283,7 +283,21 @@ static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = { > }, > }; > > +/* > + * This is a frequency table for "General Purpose" clocks. > + * These clocks can be muxed to the SoC pins and may be used by > + * external devices. They're often used as PWM source. > + * > + * See comment in gcc-mam8916.c at ftbl_gcc_gp1_3_clk. > + */ > static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { > + F(10000, P_BI_TCXO, 16, 1, 120), > + F(20000, P_BI_TCXO, 16, 1, 60), > + F(100000, P_BI_TCXO, 16, 1, 12), > + F(500000, P_GPLL0_OUT_EVEN, 12, 1, 100), > + F(1000000, P_GPLL0_OUT_EVEN, 12, 1, 50), > + F(2500000, P_GPLL0_OUT_EVEN, 12, 1, 10), > + F(5000000, P_GPLL0_OUT_EVEN, 12, 1, 5), > F(19200000, P_BI_TCXO, 1, 0, 0), > F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), > F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), > > -- > 2.39.2 >
On 6/18/24 19:50, Dmitry Baryshkov wrote: > On Tue, Jun 18, 2024 at 04:59:36PM GMT, Dzmitry Sankouski wrote: >> sdm845 has "General Purpose" clocks that can be muxed to >> SoC pins. >> >> Those clocks may be used as e.g. PWM sources for external peripherals. >> Add more frequencies to the table for those clocks so it's possible >> for arbitrary peripherals to make use of them. >> >> See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks) > > Each time I look at the table attached to the GP CLK, I feel that it's > plain wrong. In the end the GPCLK can in theory have arbitrary value > depending on the usecase. > > Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which > allow more flexibility than a default clk_rcg2_ops? If we can somehow get max m/n/d values for all possible parents, sure Konrad
On Tue, Jun 18, 2024 at 08:50:52PM GMT, Konrad Dybcio wrote: > > > On 6/18/24 19:50, Dmitry Baryshkov wrote: > > On Tue, Jun 18, 2024 at 04:59:36PM GMT, Dzmitry Sankouski wrote: > > > sdm845 has "General Purpose" clocks that can be muxed to > > > SoC pins. > > > > > > Those clocks may be used as e.g. PWM sources for external peripherals. > > > Add more frequencies to the table for those clocks so it's possible > > > for arbitrary peripherals to make use of them. > > > > > > See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks) > > > > Each time I look at the table attached to the GP CLK, I feel that it's > > plain wrong. In the end the GPCLK can in theory have arbitrary value > > depending on the usecase. > > > > Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which > > allow more flexibility than a default clk_rcg2_ops? > > If we can somehow get max m/n/d values for all possible parents, sure Calculate them at runtime?
On 6/18/24 20:55, Dmitry Baryshkov wrote: > On Tue, Jun 18, 2024 at 08:50:52PM GMT, Konrad Dybcio wrote: >> >> >> On 6/18/24 19:50, Dmitry Baryshkov wrote: >>> On Tue, Jun 18, 2024 at 04:59:36PM GMT, Dzmitry Sankouski wrote: >>>> sdm845 has "General Purpose" clocks that can be muxed to >>>> SoC pins. >>>> >>>> Those clocks may be used as e.g. PWM sources for external peripherals. >>>> Add more frequencies to the table for those clocks so it's possible >>>> for arbitrary peripherals to make use of them. >>>> >>>> See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks) >>> >>> Each time I look at the table attached to the GP CLK, I feel that it's >>> plain wrong. In the end the GPCLK can in theory have arbitrary value >>> depending on the usecase. >>> >>> Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which >>> allow more flexibility than a default clk_rcg2_ops? >> >> If we can somehow get max m/n/d values for all possible parents, sure > > Calculate them at runtime? We'd be calculating the mnd values for a frequency that's either equal or reasonably close to the one requested. My worry is that we somehow need to get the maximum values they can take (unless they're well-known) Konrad
On Tue, Jun 18, 2024 at 09:11:58PM GMT, Konrad Dybcio wrote: > > > On 6/18/24 20:55, Dmitry Baryshkov wrote: > > On Tue, Jun 18, 2024 at 08:50:52PM GMT, Konrad Dybcio wrote: > > > > > > > > > On 6/18/24 19:50, Dmitry Baryshkov wrote: > > > > On Tue, Jun 18, 2024 at 04:59:36PM GMT, Dzmitry Sankouski wrote: > > > > > sdm845 has "General Purpose" clocks that can be muxed to > > > > > SoC pins. > > > > > > > > > > Those clocks may be used as e.g. PWM sources for external peripherals. > > > > > Add more frequencies to the table for those clocks so it's possible > > > > > for arbitrary peripherals to make use of them. > > > > > > > > > > See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks) > > > > > > > > Each time I look at the table attached to the GP CLK, I feel that it's > > > > plain wrong. In the end the GPCLK can in theory have arbitrary value > > > > depending on the usecase. > > > > > > > > Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which > > > > allow more flexibility than a default clk_rcg2_ops? > > > > > > If we can somehow get max m/n/d values for all possible parents, sure > > > > Calculate them at runtime? > > We'd be calculating the mnd values for a frequency that's either equal or > reasonably close to the one requested. My worry is that we somehow need > to get the maximum values they can take (unless they're well-known) One of the options might be to force devices to use assigned-clock-parent to set GP CLK sorource and pwm-clk as an actual device using the clock.
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index ea4c3bf4fb9b..0efd3364e8f5 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -283,7 +283,21 @@ static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = { }, }; +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * See comment in gcc-mam8916.c at ftbl_gcc_gp1_3_clk. + */ static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(10000, P_BI_TCXO, 16, 1, 120), + F(20000, P_BI_TCXO, 16, 1, 60), + F(100000, P_BI_TCXO, 16, 1, 12), + F(500000, P_GPLL0_OUT_EVEN, 12, 1, 100), + F(1000000, P_GPLL0_OUT_EVEN, 12, 1, 50), + F(2500000, P_GPLL0_OUT_EVEN, 12, 1, 10), + F(5000000, P_GPLL0_OUT_EVEN, 12, 1, 5), F(19200000, P_BI_TCXO, 1, 0, 0), F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
sdm845 has "General Purpose" clocks that can be muxed to SoC pins. Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks) Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> --- drivers/clk/qcom/gcc-sdm845.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)