| Message ID | 20240619061641.5261-2-quic_kbajaj@quicinc.com (mailing list archive) |
|---|---|
| State | Queued |
| Headers | show |
| Series | qdu1000: Fix LLCC reg property | expand |
On 6/19/24 08:16, Komal Bajaj wrote: > The LLCC binding and driver was corrected to handle the stride > varying between platforms. Switch to the new format to ensure > accesses are done in the right place. > > Fixes: b0e0290bc47d ("arm64: dts: qcom: qdu1000: correct LLCC reg entries") > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> > Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 7a77f7a55498..3795ebb2d3d6 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1579,9 +1579,23 @@ gem_noc: interconnect@19100000 { system-cache-controller@19200000 { compatible = "qcom,qdu1000-llcc"; - reg = <0 0x19200000 0 0xd80000>, + reg = <0 0x19200000 0 0x80000>, + <0 0x19300000 0 0x80000>, + <0 0x19600000 0 0x80000>, + <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>, + <0 0x19b00000 0 0x80000>, + <0 0x19e00000 0 0x80000>, + <0 0x19f00000 0 0x80000>, <0 0x1a200000 0 0x80000>; reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc6_base", + "llcc7_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; };
The LLCC binding and driver was corrected to handle the stride varying between platforms. Switch to the new format to ensure accesses are done in the right place. Fixes: b0e0290bc47d ("arm64: dts: qcom: qdu1000: correct LLCC reg entries") Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com> --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.42.0