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Mon, 24 Jun 2024 06:32:43 -0700 (PDT) Received: from [192.168.1.195] ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-366f7406f4dsm1888274f8f.114.2024.06.24.06.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 06:32:43 -0700 (PDT) From: Srinivas Kandagatla Date: Mon, 24 Jun 2024 14:32:38 +0100 Subject: [PATCH v2 3/3] arm64: dts: qcom: x1e80100: add soundwire controller resets Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-x1e-swr-reset-v2-3-8bc677fcfa64@linaro.org> References: <20240624-x1e-swr-reset-v2-0-8bc677fcfa64@linaro.org> In-Reply-To: <20240624-x1e-swr-reset-v2-0-8bc677fcfa64@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2919; i=srinivas.kandagatla@linaro.org; h=from:subject:message-id; bh=eN0nSauQHWzcpR3ztkX7wbxGkq9GOgpa8mxkvBiq8XY=; b=owEBbQGS/pANAwAKAXqh/VnHNFU3AcsmYgBmeXV3JmURE/5lysOEoqtpbe95ged/33DXxhuI2 4zfPndTSOiJATMEAAEKAB0WIQQi509axvzi9vce3Y16of1ZxzRVNwUCZnl1dwAKCRB6of1ZxzRV NyRZB/9jIVWgTzLtdOV1vvd9C6m8ZdWzEiZwaINjLMXUxmzQNXLVdfwEs/wUfn+P54aCLEjEbky +lBO0MJ+MUnwDQ44QfxkX633WqFSV0ce3XiRqAf3QNwAAzLgPyUdjFjEwD1jJwo1Q3DSBAc8nuy SvPw657GNW5W+tMkkOFSVR8pKFuTVvDJ8cV25fmJBZHLAd6JrMd/y/Ae9KgQg25DdXurCyXyGC5 ymG1grMxf3EAHxd+l4Cx3UHEBhX4eHV5OlX5GnysFocqt4U7hZFxfM5XzN0bLzo0ALW7PZHD/KX PWjDs9fyoLWEar2C8/sCC8UhlIeGX/KIF9xq+cu2zEhJjIgy X-Developer-Key: i=srinivas.kandagatla@linaro.org; a=openpgp; fpr=ED6472765AB36EC43B3EF97AD77E3FC0562560D6 Soundwire controllers (WSA, WSA2, RX, TX) require reset lines to enable switching clock control from hardware to software. Add them along with the reset control providers. Without this reset we might hit fifo under/over run when we try to write to soundwire device registers. Signed-off-by: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 09fd6c8e53bb..fa28dbdd1419 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -3177,6 +3178,8 @@ swr3: soundwire@6ab0000 { pinctrl-0 = <&wsa2_swr_active>; pinctrl-names = "default"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; + reset-names = "swr_audio_cgcr"; qcom,din-ports = <4>; qcom,dout-ports = <9>; @@ -3225,6 +3228,8 @@ swr1: soundwire@6ad0000 { pinctrl-0 = <&rx_swr_active>; pinctrl-names = "default"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; qcom,din-ports = <1>; qcom,dout-ports = <11>; @@ -3289,6 +3294,8 @@ swr0: soundwire@6b10000 { pinctrl-0 = <&wsa_swr_active>; pinctrl-names = "default"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names = "swr_audio_cgcr"; qcom,din-ports = <4>; qcom,dout-ports = <9>; @@ -3309,6 +3316,13 @@ swr0: soundwire@6b10000 { status = "disabled"; }; + lpass_audiocc: clock-controller@6b6c000 { + compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; + reg = <0 0x06b6c000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + swr2: soundwire@6d30000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06d30000 0 0x10000>; @@ -3318,6 +3332,8 @@ swr2: soundwire@6d30000 { ; interrupt-names = "core", "wakeup"; label = "TX"; + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; pinctrl-0 = <&tx_swr_active>; pinctrl-names = "default"; @@ -3474,6 +3490,13 @@ data-pins { }; }; + lpasscc: clock-controller@6ea0000 { + compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; + reg = <0 0x06ea0000 0 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,x1e80100-lpass-ag-noc"; reg = <0 0x7e40000 0 0xE080>;