| Message ID | 20240626143020.3682243-7-quic_bibekkum@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs | expand |
Hi Bibek, kernel test robot noticed the following build warnings: [auto build test WARNING on joro-iommu/next] [also build test WARNING on linus/master v6.10-rc5 next-20240627] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Bibek-Kumar-Patro/iommu-arm-smmu-re-enable-context-caching-in-smmu-reset-operation/20240627-074037 base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next patch link: https://lore.kernel.org/r/20240626143020.3682243-7-quic_bibekkum%40quicinc.com patch subject: [PATCH v12 6/6] iommu/arm-smmu: add support for PRR bit setup config: arm64-randconfig-r113-20240628 (https://download.01.org/0day-ci/archive/20240628/202406281241.xEX0TWjt-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 13.2.0 reproduce: (https://download.01.org/0day-ci/archive/20240628/202406281241.xEX0TWjt-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406281241.xEX0TWjt-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:247:54: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:247:54: sparse: expected void volatile [noderef] __iomem *addr drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:247:54: sparse: got void * drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:250:54: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:250:54: sparse: expected void volatile [noderef] __iomem *addr drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:250:54: sparse: got void * drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c: note: in included file (through include/linux/mmzone.h, include/linux/gfp.h, include/linux/slab.h, ...): include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false vim +247 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c 238 239 static void qcom_adreno_smmu_set_prr(const void *cookie, phys_addr_t page_addr, bool set) 240 { 241 struct arm_smmu_domain *smmu_domain = (void *)cookie; 242 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 243 struct arm_smmu_device *smmu = smmu_domain->smmu; 244 u32 reg = 0; 245 246 writel_relaxed(lower_32_bits(page_addr), > 247 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR); 248 249 writel_relaxed(upper_32_bits(page_addr), 250 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR); 251 252 reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR); 253 reg &= ~GFX_ACTLR_PRR; 254 if (set) 255 reg |= FIELD_PREP(GFX_ACTLR_PRR, 1); 256 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg); 257
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index bd101a161d04..752f909d26b6 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -28,6 +28,7 @@ #define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT) #define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) #define PREFETCH_DEEP (3 << PREFETCH_SHIFT) +#define GFX_ACTLR_PRR (1 << 5) static const struct actlr_config sc7280_apps_actlr_cfg[] = { { 0x0800, 0x04e0, PREFETCH_DEFAULT | CMTLB }, @@ -235,6 +236,27 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); } +static void qcom_adreno_smmu_set_prr(const void *cookie, phys_addr_t page_addr, bool set) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu = smmu_domain->smmu; + u32 reg = 0; + + writel_relaxed(lower_32_bits(page_addr), + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR); + + writel_relaxed(upper_32_bits(page_addr), + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR); + + reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR); + reg &= ~GFX_ACTLR_PRR; + if (set) + reg |= FIELD_PREP(GFX_ACTLR_PRR, 1); + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg); + +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -407,6 +429,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->get_fault_info = qcom_adreno_smmu_get_fault_info; priv->set_stall = qcom_adreno_smmu_set_stall; priv->resume_translation = qcom_adreno_smmu_resume_translation; + priv->set_prr = qcom_adreno_smmu_set_prr; actlrvar = qsmmu->data->actlrvar; if (!actlrvar) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index d9c2ef8c1653..3076bef49e20 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -154,6 +154,8 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_SCTLR_M BIT(0) #define ARM_SMMU_CB_ACTLR 0x4 +#define ARM_SMMU_GFX_PRR_CFG_LADDR 0x6008 +#define ARM_SMMU_GFX_PRR_CFG_UADDR 0x600C #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_RESUME_TERMINATE BIT(0) diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index c637e0997f6d..d6e2ca9f8d8c 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -49,7 +49,10 @@ struct adreno_smmu_fault_info { * before set_ttbr0_cfg(). If stalling on fault is enabled, * the GPU driver must call resume_translation() * @resume_translation: Resume translation after a fault - * + * @set_prr: Extendible interface to be used by GPU to modify the + * ACTLR register bits, currently used to configure + * Partially-Resident-Region (PRR) feature's + * setup and reset sequence as requested. * * The GPU driver (drm/msm) and adreno-smmu work together for controlling * the GPU's SMMU instance. This is by necessity, as the GPU is directly @@ -67,6 +70,7 @@ struct adreno_smmu_priv { void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); void (*set_stall)(const void *cookie, bool enabled); void (*resume_translation)(const void *cookie, bool terminate); + void (*set_prr)(const void *cookie, phys_addr_t page_addr, bool set); }; #endif /* __ADRENO_SMMU_PRIV_H */
Add an adreno-smmu-priv interface for drm/msm to call into arm-smmu-qcom and initiate the PRR bit setup or reset sequence as per request. This will be used by GPU to setup the PRR bit and related configuration registers through adreno-smmu private interface instead of directly poking the smmu hardware. Suggested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com> --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 23 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ include/linux/adreno-smmu-priv.h | 6 +++++- 3 files changed, 30 insertions(+), 1 deletion(-) -- 2.34.1