| Message ID | 20240626143302.810632-7-quic_devipriy@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add NSS clock controller support for IPQ9574 | expand |
On Wed, Jun 26, 2024 at 08:03:01PM GMT, Devi Priya wrote: > Add a node for the nss clock controller found on ipq9574 based devices. > > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > Changes in V5: > - Dropped interconnects from nsscc node and added > interconnect-cells to NSS clock provider so that it can be used > as icc provider. > > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 41 +++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 48dfafea46a7..b6f8800bf63c 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -11,6 +11,8 @@ > #include <dt-bindings/interconnect/qcom,ipq9574.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/reset/qcom,ipq9574-gcc.h> > +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h> > +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h> > #include <dt-bindings/thermal/thermal.h> > > / { > @@ -19,6 +21,24 @@ / { > #size-cells = <2>; > > clocks { > + bias_pll_cc_clk: bias-pll-cc-clk { > + compatible = "fixed-clock"; > + clock-frequency = <1200000000>; > + #clock-cells = <0>; > + }; > + > + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk { > + compatible = "fixed-clock"; > + clock-frequency = <461500000>; > + #clock-cells = <0>; > + }; > + > + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { > + compatible = "fixed-clock"; > + clock-frequency = <353000000>; > + #clock-cells = <0>; > + }; What is the source for these clocks? Is it really an on-board crystal? > + > sleep_clk: sleep-clk { > compatible = "fixed-clock"; > #clock-cells = <0>; d
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 48dfafea46a7..b6f8800bf63c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -11,6 +11,8 @@ #include <dt-bindings/interconnect/qcom,ipq9574.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h> #include <dt-bindings/thermal/thermal.h> / { @@ -19,6 +21,24 @@ / { #size-cells = <2>; clocks { + bias_pll_cc_clk: bias-pll-cc-clk { + compatible = "fixed-clock"; + clock-frequency = <1200000000>; + #clock-cells = <0>; + }; + + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk { + compatible = "fixed-clock"; + clock-frequency = <461500000>; + #clock-cells = <0>; + }; + + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { + compatible = "fixed-clock"; + clock-frequency = <353000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -756,6 +776,27 @@ frame@b128000 { status = "disabled"; }; }; + + nsscc: clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&xo_board_clk>, + <&bias_pll_cc_clk>, + <&bias_pll_nss_noc_clk>, + <&bias_pll_ubi_nc_clk>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + #interconnect-cells = <1>; + }; }; thermal-zones {
Add a node for the nss clock controller found on ipq9574 based devices. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- Changes in V5: - Dropped interconnects from nsscc node and added interconnect-cells to NSS clock provider so that it can be used as icc provider. arch/arm64/boot/dts/qcom/ipq9574.dtsi | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)