| Message ID | 20240711100038.268803-5-vladimir.lypak@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | fixes for Adreno A5Xx preemption | expand |
On Thu, Jul 11, 2024 at 10:00:21AM +0000, Vladimir Lypak wrote: > There is another cause for soft lock-up of GPU in empty ring-buffer: > race between GPU executing last commands and CPU checking ring for > emptiness. On GPU side IRQ for retire is triggered by CACHE_FLUSH_TS > event and RPTR shadow (which is used to check ring emptiness) is updated > a bit later from CP_CONTEXT_SWITCH_YIELD. Thus if GPU is executing its > last commands slow enough or we check that ring too fast we will miss a > chance to trigger switch to lower priority ring because current ring isn't > empty just yet. This can escalate to lock-up situation described in > previous patch. > To work-around this issue we keep track of last submit sequence number > for each ring and compare it with one written to memptrs from GPU during > execution of CACHE_FLUSH_TS event. > This is interesting! Is this just theoretical or are you able to hit this race on your device (after picking other fixes in this series)? -Akhil. > Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets") > Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++++ > drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 1 + > drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 4 ++++ > 3 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index 266744ee1d5f..001f11f5febc 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -65,6 +65,8 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > > static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) > { > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); > struct msm_ringbuffer *ring = submit->ring; > struct drm_gem_object *obj; > uint32_t *ptr, dwords; > @@ -109,6 +111,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit > } > } > > + a5xx_gpu->last_seqno[ring->id] = submit->seqno; > a5xx_flush(gpu, ring, true); > a5xx_preempt_trigger(gpu, true); > > @@ -210,6 +213,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) > /* Write the fence to the scratch register */ > OUT_PKT4(ring, REG_A5XX_CP_SCRATCH_REG(2), 1); > OUT_RING(ring, submit->seqno); > + a5xx_gpu->last_seqno[ring->id] = submit->seqno; > > /* > * Execute a CACHE_FLUSH_TS event. This will ensure that the > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h > index 1120824853d4..7269eaab9a7a 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h > @@ -34,6 +34,7 @@ struct a5xx_gpu { > struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS]; > struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS]; > uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; > + uint32_t last_seqno[MSM_GPU_MAX_RINGS]; > > atomic_t preempt_state; > struct timer_list preempt_timer; > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > index f8d09a83c5ae..6bd92f9b2338 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > @@ -55,6 +55,8 @@ static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > /* Return the highest priority ringbuffer with something in it */ > static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) > { > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); > unsigned long flags; > int i; > > @@ -64,6 +66,8 @@ static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) > > spin_lock_irqsave(&ring->preempt_lock, flags); > empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); > + if (!empty && ring == a5xx_gpu->cur_ring) > + empty = ring->memptrs->fence == a5xx_gpu->last_seqno[i]; > spin_unlock_irqrestore(&ring->preempt_lock, flags); > > if (!empty) > -- > 2.45.2 >
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 266744ee1d5f..001f11f5febc 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -65,6 +65,8 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); struct msm_ringbuffer *ring = submit->ring; struct drm_gem_object *obj; uint32_t *ptr, dwords; @@ -109,6 +111,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit } } + a5xx_gpu->last_seqno[ring->id] = submit->seqno; a5xx_flush(gpu, ring, true); a5xx_preempt_trigger(gpu, true); @@ -210,6 +213,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) /* Write the fence to the scratch register */ OUT_PKT4(ring, REG_A5XX_CP_SCRATCH_REG(2), 1); OUT_RING(ring, submit->seqno); + a5xx_gpu->last_seqno[ring->id] = submit->seqno; /* * Execute a CACHE_FLUSH_TS event. This will ensure that the diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h index 1120824853d4..7269eaab9a7a 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h @@ -34,6 +34,7 @@ struct a5xx_gpu { struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS]; struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS]; uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; + uint32_t last_seqno[MSM_GPU_MAX_RINGS]; atomic_t preempt_state; struct timer_list preempt_timer; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c index f8d09a83c5ae..6bd92f9b2338 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c @@ -55,6 +55,8 @@ static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) /* Return the highest priority ringbuffer with something in it */ static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); unsigned long flags; int i; @@ -64,6 +66,8 @@ static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) spin_lock_irqsave(&ring->preempt_lock, flags); empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); + if (!empty && ring == a5xx_gpu->cur_ring) + empty = ring->memptrs->fence == a5xx_gpu->last_seqno[i]; spin_unlock_irqrestore(&ring->preempt_lock, flags); if (!empty)
There is another cause for soft lock-up of GPU in empty ring-buffer: race between GPU executing last commands and CPU checking ring for emptiness. On GPU side IRQ for retire is triggered by CACHE_FLUSH_TS event and RPTR shadow (which is used to check ring emptiness) is updated a bit later from CP_CONTEXT_SWITCH_YIELD. Thus if GPU is executing its last commands slow enough or we check that ring too fast we will miss a chance to trigger switch to lower priority ring because current ring isn't empty just yet. This can escalate to lock-up situation described in previous patch. To work-around this issue we keep track of last submit sequence number for each ring and compare it with one written to memptrs from GPU during execution of CACHE_FLUSH_TS event. Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++++ drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 4 ++++ 3 files changed, 9 insertions(+)