| Message ID | 20240716-topic-sm8650-upstream-fix-dispcc-v3-1-5bfd56c899da@linaro.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | clk: qcom: dispcc-sm8650: round of fixes | expand |
On 16.07.2024 11:05 AM, Neil Armstrong wrote: > The RCG's clk src has to be parked at XO while disabling as per the > HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. > > It also changes dptx1_aux_clk_src to use the correct ops instead of > clk_dp_ops. > > Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On Tue, Jul 16, 2024 at 11:05:21AM GMT, Neil Armstrong wrote: > The RCG's clk src has to be parked at XO while disabling as per the > HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. > > It also changes dptx1_aux_clk_src to use the correct ops instead of > clk_dp_ops. > > Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/clk/qcom/dispcc-sm8650.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c > index c9d2751f5cb8..80fe25afccf7 100644 > --- a/drivers/clk/qcom/dispcc-sm8650.c > +++ b/drivers/clk/qcom/dispcc-sm8650.c > @@ -398,7 +398,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_dp_ops, > + .ops = &clk_rcg2_ops, Should this also be clk_rcg2_shared_ops ? > }, > }; > > @@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { > .parent_data = disp_cc_parent_data_5, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -575,7 +575,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { > .parent_data = disp_cc_parent_data_5, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > > -- > 2.34.1 >
On 16/07/2024 13:40, Dmitry Baryshkov wrote: > On Tue, Jul 16, 2024 at 11:05:21AM GMT, Neil Armstrong wrote: >> The RCG's clk src has to be parked at XO while disabling as per the >> HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. >> >> It also changes dptx1_aux_clk_src to use the correct ops instead of >> clk_dp_ops. >> >> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> drivers/clk/qcom/dispcc-sm8650.c | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c >> index c9d2751f5cb8..80fe25afccf7 100644 >> --- a/drivers/clk/qcom/dispcc-sm8650.c >> +++ b/drivers/clk/qcom/dispcc-sm8650.c >> @@ -398,7 +398,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_dp_ops, >> + .ops = &clk_rcg2_ops, > > Should this also be clk_rcg2_shared_ops ? Nop, the only parent is tcxo > >> }, >> }; >> >> @@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { >> .parent_data = disp_cc_parent_data_5, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -575,7 +575,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { >> .parent_data = disp_cc_parent_data_5, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> >> -- >> 2.34.1 >> >
diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c index c9d2751f5cb8..80fe25afccf7 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -398,7 +398,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_dp_ops, + .ops = &clk_rcg2_ops, }, }; @@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -575,7 +575,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, };
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. It also changes dptx1_aux_clk_src to use the correct ops instead of clk_dp_ops. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/clk/qcom/dispcc-sm8650.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)