| Message ID | 20240729231259.2122976-5-quic_amelende@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | thermal: qcom-spmi-temp-alarm: add support for new TEMP_ALARM subtypes | expand |
On Mon, Jul 29, 2024 at 04:12:58PM GMT, Anjelique Melendez wrote: > Add support for TEMP_ALARM GEN2 PMIC peripherals with digital major > revision 2. This revision utilizes individual temp DAC registers > to set the threshold temperature for over-temperature stages 1, > 2, and 3 instead of a single register to specify a set of > thresholds. > > Co-developed-by: David Collins <quic_collinsd@quicinc.com> > Signed-off-by: David Collins <quic_collinsd@quicinc.com> > Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> > --- > drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 195 ++++++++++++++++++-- > 1 file changed, 184 insertions(+), 11 deletions(-) > > diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c > index de4a2d99f0d5..1f56acd8f637 100644 > --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c > +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c > @@ -24,6 +24,10 @@ > #define QPNP_TM_REG_STATUS 0x08 > #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 > #define QPNP_TM_REG_ALARM_CTRL 0x46 > +/* TEMP_DAC_* registers are only present for TEMP_GEN2 v2.0 */ > +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 > +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 > +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 > > #define QPNP_TM_TYPE 0x09 > #define QPNP_TM_SUBTYPE_GEN1 0x08 > @@ -65,13 +69,42 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = { > > #define TEMP_STAGE_HYSTERESIS 2000 > > +/* > + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the threshold > + * for each stage independently. > + * TEMP_DAC_STG* = 0 --> 80 C > + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC). > + */ > +#define TEMP_DAC_MIN 80000 > +#define TEMP_DAC_SCALE_NUM 8 > +#define TEMP_DAC_SCALE_DEN 5000 > + > +#define TEMP_DAC_TEMP_TO_REG(temp) \ > + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) > +#define TEMP_DAC_REG_TO_TEMP(reg) \ > + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) > + > +static const long temp_dac_max[STAGE_COUNT] = { > + 119375, 159375, 159375 > +}; > + > /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ > #define DEFAULT_TEMP 37000 > > +struct qpnp_tm_chip; > + > +struct spmi_temp_alarm_data { > + const struct thermal_zone_device_ops *ops; > + bool has_temp_dac; > + int (*setup)(struct qpnp_tm_chip *chip); > + int (*update_trip_temps)(struct qpnp_tm_chip *chip); > +}; > + > struct qpnp_tm_chip { > struct regmap *map; > struct device *dev; > struct thermal_zone_device *tz_dev; > + const struct spmi_temp_alarm_data *data; > unsigned int subtype; > unsigned int dig_revision; > long temp; > @@ -85,6 +118,8 @@ struct qpnp_tm_chip { > > struct iio_channel *adc; > const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; > + > + long temp_dac_map[STAGE_COUNT]; > }; > > /* This array maps from GEN2 alarm state to GEN1 alarm stage */ > @@ -118,6 +153,13 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data) > */ > static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) > { > + if (chip->data->has_temp_dac) { > + if (stage == 0 || stage > STAGE_COUNT) > + return 0; > + > + return chip->temp_dac_map[stage - 1]; > + } > + > if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || > stage > STAGE_COUNT) > return 0; > @@ -219,6 +261,34 @@ static int qpnp_tm_get_temp(struct thermal_zone_device *tz, int *temp) > return 0; > } > > +static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, int trip, > + int temp) > +{ > + int ret, temp_cfg; > + u8 reg; > + > + if (trip < 0 || trip >= STAGE_COUNT) { > + dev_err(chip->dev, "invalid TEMP_DAC trip = %d\n", trip); > + return -EINVAL; > + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { > + dev_err(chip->dev, "invalid TEMP_DAC temp = %d\n", temp); > + return -EINVAL; > + } > + > + reg = TEMP_DAC_TEMP_TO_REG(temp); > + temp_cfg = TEMP_DAC_REG_TO_TEMP(reg); > + > + ret = qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); > + if (ret < 0) { > + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=%d\n", ret); > + return ret; > + } > + > + chip->temp_dac_map[trip] = temp_cfg; > + > + return 0; > +} > + > static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, > int temp) > { > @@ -286,6 +356,24 @@ static const struct thermal_zone_device_ops qpnp_tm_sensor_ops = { > .set_trip_temp = qpnp_tm_set_trip_temp, > }; > > +static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz, > + int trip, int temp) > +{ > + struct qpnp_tm_chip *chip = tz->devdata; > + int ret; > + > + mutex_lock(&chip->lock); > + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip, temp); > + mutex_unlock(&chip->lock); > + > + return ret; > +} > + > +static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = { > + .get_temp = qpnp_tm_get_temp, > + .set_trip_temp = qpnp_tm_gen2_rev2_set_trip_temp, > +}; > + > static irqreturn_t qpnp_tm_isr(int irq, void *data) > { > struct qpnp_tm_chip *chip = data; > @@ -313,6 +401,71 @@ static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip) > return THERMAL_TEMP_INVALID; > } > > +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ > +static int qpnp_tm_gen2_rev2_update_trip_temps(struct qpnp_tm_chip *chip) > +{ > + struct thermal_trip trip = {0}; > + int ret, ntrips, i; > + > + ntrips = thermal_zone_get_num_trips(chip->tz_dev); > + /* Keep hardware defaults if no DT trips are defined. */ > + if (ntrips <= 0) > + return 0; > + > + for (i = 0; i < ntrips; i++) { > + ret = thermal_zone_get_trip(chip->tz_dev, i, &trip); > + if (ret < 0) > + return ret; > + > + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, i, trip.temperature); > + if (ret < 0) > + return ret; > + } > + > + /* Verify that trips are strictly increasing. */ There is no such requirement in the DT bindings. Please don't invent artificial restrictions, especially if they are undocumented. > + for (i = 1; i < STAGE_COUNT; i++) { > + if (chip->temp_dac_map[i] <= chip->temp_dac_map[i - 1]) { > + dev_err(chip->dev, "Threshold %d=%ld <= threshold %d=%ld\n", > + i, chip->temp_dac_map[i], i - 1, > + chip->temp_dac_map[i - 1]); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > +/* Read the hardware default TEMP_DAC stage threshold temperatures */ > +static int qpnp_tm_gen2_rev2_init(struct qpnp_tm_chip *chip) > +{ > + int ret, i; > + u8 reg = 0; > + > + for (i = 0; i < STAGE_COUNT; i++) { > + ret = qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); > + if (ret < 0) > + return ret; > + > + chip->temp_dac_map[i] = TEMP_DAC_REG_TO_TEMP(reg); > + } > + > + return 0; > +} > + > +static const struct spmi_temp_alarm_data spmi_temp_alarm_data = { > + .ops = &qpnp_tm_sensor_ops, > + .has_temp_dac = false, > + .setup = NULL, > + .update_trip_temps = NULL, No need to init to NULL, that's the default (and false too). > +}; > + > +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = { > + .ops = &qpnp_tm_gen2_rev2_sensor_ops, > + .has_temp_dac = true, > + .setup = qpnp_tm_gen2_rev2_init, > + .update_trip_temps = qpnp_tm_gen2_rev2_update_trip_temps, > +}; > + > /* > * This function initializes the internal temp value based on only the > * current thermal stage and threshold. Setup threshold control and > @@ -339,21 +492,27 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) > goto out; > chip->stage = ret; > > - stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1 > + stage = (chip->subtype == QPNP_TM_SUBTYPE_GEN1) > ? chip->stage : alarm_state_map[chip->stage]; > > if (stage) > chip->temp = qpnp_tm_decode_temp(chip, stage); > > - mutex_unlock(&chip->lock); > + if (chip->data->update_trip_temps) { > + ret = chip->data->update_trip_temps(chip); > + if (ret < 0) > + goto out; > + } else { > + mutex_unlock(&chip->lock); > > - crit_temp = qpnp_tm_get_critical_trip_temp(chip); > + crit_temp = qpnp_tm_get_critical_trip_temp(chip); > > - mutex_lock(&chip->lock); > + mutex_lock(&chip->lock); > > - ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); > - if (ret < 0) > - goto out; > + ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); > + if (ret < 0) > + goto out; Can you move this to the update_trip_temps() callback? Then there is no need to have ifs here. > + } > > /* Enable the thermal alarm PMIC module in always-on mode. */ > reg = ALARM_CTRL_FORCE_ENABLE; > @@ -380,6 +539,10 @@ static int qpnp_tm_probe(struct platform_device *pdev) > if (!chip) > return -ENOMEM; > > + chip->data = of_device_get_match_data(&pdev->dev); > + if (!chip->data) > + return -EINVAL; > + > dev_set_drvdata(&pdev->dev, chip); > chip->dev = &pdev->dev; > > @@ -455,18 +618,21 @@ static int qpnp_tm_probe(struct platform_device *pdev) > } > > chip->subtype = subtype; > - if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) > + if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major == 1) > chip->temp_map = &temp_map_gen2_v1; > - else > + else if (subtype == QPNP_TM_SUBTYPE_GEN1) > chip->temp_map = &temp_map_gen1; If you already have per-compatible match data, why do you need to have check revisions? Please be consistent. > > + if (chip->data->setup) > + chip->data->setup(chip); > + > /* > * Register the sensor before initializing the hardware to be able to > * read the trip points. get_temp() returns the default temperature > * before the hardware initialization is completed. > */ > chip->tz_dev = devm_thermal_of_zone_register( > - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); > + &pdev->dev, 0, chip, chip->data->ops); > if (IS_ERR(chip->tz_dev)) > return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev), > "failed to register sensor\n"); > @@ -488,7 +654,14 @@ static int qpnp_tm_probe(struct platform_device *pdev) > } > > static const struct of_device_id qpnp_tm_match_table[] = { > - { .compatible = "qcom,spmi-temp-alarm" }, > + { > + .compatible = "qcom,spmi-temp-alarm", > + .data = &spmi_temp_alarm_data, > + }, > + { > + .compatible = "qcom,spmi-temp-alarm-gen2-rev2", > + .data = &spmi_temp_alarm_gen2_rev2_data, > + }, > { } > }; > MODULE_DEVICE_TABLE(of, qpnp_tm_match_table); > -- > 2.34.1 >
>> >> +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ >> +static int qpnp_tm_gen2_rev2_update_trip_temps(struct qpnp_tm_chip *chip) >> +{ >> + struct thermal_trip trip = {0}; >> + int ret, ntrips, i; >> + >> + ntrips = thermal_zone_get_num_trips(chip->tz_dev); >> + /* Keep hardware defaults if no DT trips are defined. */ >> + if (ntrips <= 0) >> + return 0; >> + >> + for (i = 0; i < ntrips; i++) { >> + ret = thermal_zone_get_trip(chip->tz_dev, i, &trip); >> + if (ret < 0) >> + return ret; >> + >> + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, i, trip.temperature); >> + if (ret < 0) >> + return ret; >> + } >> + >> + /* Verify that trips are strictly increasing. */ > > There is no such requirement in the DT bindings. Please don't invent > artificial restrictions, especially if they are undocumented. > This is not an entirely new restirction. Currently the temp alarm driver has hardcoded temperature thresholds options which are "strictly increasing" (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/thermal/qcom/qcom-spmi-temp-alarm.c?h=v6.11-rc1#n44). The threshold values are initially configured based on the stage 2 critical trip temperature. For newer PMICs, we have individual temperature registers for stage 1, 2, and 3, so we instead configure each threshold temperature as defined in DT. In general since stage 1 = warning, stage 2 = system should shut down, stage 3 = emergency shutdown, we would expect for temperature thresholds to increase for each stage (https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/thermal?h=v5.4.281&id=f1599f9e4cd6f1dd0cad202853fb830854f4e944). I agree that we are missing some documentation but since the trips are defined in the thermal_zone node what is the best way to mention this requirement? Will adding a few sentences to qcom,spmi-temp-alarm.yaml description be enough? Do we need to make changes to thermal_zone.yaml so that dt_binding_check catches this requirement? >> + for (i = 1; i < STAGE_COUNT; i++) { >> + if (chip->temp_dac_map[i] <= chip->temp_dac_map[i - 1]) { >> + dev_err(chip->dev, "Threshold %d=%ld <= threshold %d=%ld\n", >> + i, chip->temp_dac_map[i], i - 1, >> + chip->temp_dac_map[i - 1]); >> + return -EINVAL; >> + } >> + } >> + >> + return 0; Thanks, Anjelique
On Wed, 31 Jul 2024 at 01:44, Anjelique Melendez <quic_amelende@quicinc.com> wrote: > > >> > >> +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ > >> +static int qpnp_tm_gen2_rev2_update_trip_temps(struct qpnp_tm_chip *chip) > >> +{ > >> + struct thermal_trip trip = {0}; > >> + int ret, ntrips, i; > >> + > >> + ntrips = thermal_zone_get_num_trips(chip->tz_dev); > >> + /* Keep hardware defaults if no DT trips are defined. */ > >> + if (ntrips <= 0) > >> + return 0; > >> + > >> + for (i = 0; i < ntrips; i++) { > >> + ret = thermal_zone_get_trip(chip->tz_dev, i, &trip); > >> + if (ret < 0) > >> + return ret; > >> + > >> + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, i, trip.temperature); > >> + if (ret < 0) > >> + return ret; > >> + } > >> + > >> + /* Verify that trips are strictly increasing. */ > > > > There is no such requirement in the DT bindings. Please don't invent > > artificial restrictions, especially if they are undocumented. > > > > This is not an entirely new restirction. Currently the temp alarm driver > has hardcoded temperature thresholds options which are "strictly increasing" > (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/thermal/qcom/qcom-spmi-temp-alarm.c?h=v6.11-rc1#n44). > The threshold values are initially configured based on the stage 2 critical trip > temperature. > For newer PMICs, we have individual temperature registers for stage 1, 2, and 3, > so we instead configure each threshold temperature as defined in DT. In general > since stage 1 = warning, stage 2 = system should shut down, stage 3 = emergency shutdown, > we would expect for temperature thresholds to increase for each stage > (https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/thermal?h=v5.4.281&id=f1599f9e4cd6f1dd0cad202853fb830854f4e944). > > I agree that we are missing some documentation but since the trips are defined in the > thermal_zone node what is the best way to mention this requirement? Will adding a > few sentences to qcom,spmi-temp-alarm.yaml description be enough? Do we need > to make changes to thermal_zone.yaml so that dt_binding_check catches this requirement? In my opinion the driver needs to be fixed to compile the state after looking at all trip points, but Daniel / Amit / Thara can have a more qualified opinion. > > >> + for (i = 1; i < STAGE_COUNT; i++) { > >> + if (chip->temp_dac_map[i] <= chip->temp_dac_map[i - 1]) { > >> + dev_err(chip->dev, "Threshold %d=%ld <= threshold %d=%ld\n", > >> + i, chip->temp_dac_map[i], i - 1, > >> + chip->temp_dac_map[i - 1]); > >> + return -EINVAL; > >> + } > >> + } > >> + > >> + return 0; > Thanks, > Anjelique
diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index de4a2d99f0d5..1f56acd8f637 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -24,6 +24,10 @@ #define QPNP_TM_REG_STATUS 0x08 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 +/* TEMP_DAC_* registers are only present for TEMP_GEN2 v2.0 */ +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 @@ -65,13 +69,42 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = { #define TEMP_STAGE_HYSTERESIS 2000 +/* + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the threshold + * for each stage independently. + * TEMP_DAC_STG* = 0 --> 80 C + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC). + */ +#define TEMP_DAC_MIN 80000 +#define TEMP_DAC_SCALE_NUM 8 +#define TEMP_DAC_SCALE_DEN 5000 + +#define TEMP_DAC_TEMP_TO_REG(temp) \ + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) +#define TEMP_DAC_REG_TO_TEMP(reg) \ + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) + +static const long temp_dac_max[STAGE_COUNT] = { + 119375, 159375, 159375 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ #define DEFAULT_TEMP 37000 +struct qpnp_tm_chip; + +struct spmi_temp_alarm_data { + const struct thermal_zone_device_ops *ops; + bool has_temp_dac; + int (*setup)(struct qpnp_tm_chip *chip); + int (*update_trip_temps)(struct qpnp_tm_chip *chip); +}; + struct qpnp_tm_chip { struct regmap *map; struct device *dev; struct thermal_zone_device *tz_dev; + const struct spmi_temp_alarm_data *data; unsigned int subtype; unsigned int dig_revision; long temp; @@ -85,6 +118,8 @@ struct qpnp_tm_chip { struct iio_channel *adc; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + + long temp_dac_map[STAGE_COUNT]; }; /* This array maps from GEN2 alarm state to GEN1 alarm stage */ @@ -118,6 +153,13 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data) */ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) { + if (chip->data->has_temp_dac) { + if (stage == 0 || stage > STAGE_COUNT) + return 0; + + return chip->temp_dac_map[stage - 1]; + } + if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || stage > STAGE_COUNT) return 0; @@ -219,6 +261,34 @@ static int qpnp_tm_get_temp(struct thermal_zone_device *tz, int *temp) return 0; } +static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, int trip, + int temp) +{ + int ret, temp_cfg; + u8 reg; + + if (trip < 0 || trip >= STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_DAC trip = %d\n", trip); + return -EINVAL; + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { + dev_err(chip->dev, "invalid TEMP_DAC temp = %d\n", temp); + return -EINVAL; + } + + reg = TEMP_DAC_TEMP_TO_REG(temp); + temp_cfg = TEMP_DAC_REG_TO_TEMP(reg); + + ret = qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); + if (ret < 0) { + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=%d\n", ret); + return ret; + } + + chip->temp_dac_map[trip] = temp_cfg; + + return 0; +} + static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, int temp) { @@ -286,6 +356,24 @@ static const struct thermal_zone_device_ops qpnp_tm_sensor_ops = { .set_trip_temp = qpnp_tm_set_trip_temp, }; +static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz, + int trip, int temp) +{ + struct qpnp_tm_chip *chip = tz->devdata; + int ret; + + mutex_lock(&chip->lock); + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = { + .get_temp = qpnp_tm_get_temp, + .set_trip_temp = qpnp_tm_gen2_rev2_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip = data; @@ -313,6 +401,71 @@ static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip) return THERMAL_TEMP_INVALID; } +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ +static int qpnp_tm_gen2_rev2_update_trip_temps(struct qpnp_tm_chip *chip) +{ + struct thermal_trip trip = {0}; + int ret, ntrips, i; + + ntrips = thermal_zone_get_num_trips(chip->tz_dev); + /* Keep hardware defaults if no DT trips are defined. */ + if (ntrips <= 0) + return 0; + + for (i = 0; i < ntrips; i++) { + ret = thermal_zone_get_trip(chip->tz_dev, i, &trip); + if (ret < 0) + return ret; + + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, i, trip.temperature); + if (ret < 0) + return ret; + } + + /* Verify that trips are strictly increasing. */ + for (i = 1; i < STAGE_COUNT; i++) { + if (chip->temp_dac_map[i] <= chip->temp_dac_map[i - 1]) { + dev_err(chip->dev, "Threshold %d=%ld <= threshold %d=%ld\n", + i, chip->temp_dac_map[i], i - 1, + chip->temp_dac_map[i - 1]); + return -EINVAL; + } + } + + return 0; +} + +/* Read the hardware default TEMP_DAC stage threshold temperatures */ +static int qpnp_tm_gen2_rev2_init(struct qpnp_tm_chip *chip) +{ + int ret, i; + u8 reg = 0; + + for (i = 0; i < STAGE_COUNT; i++) { + ret = qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); + if (ret < 0) + return ret; + + chip->temp_dac_map[i] = TEMP_DAC_REG_TO_TEMP(reg); + } + + return 0; +} + +static const struct spmi_temp_alarm_data spmi_temp_alarm_data = { + .ops = &qpnp_tm_sensor_ops, + .has_temp_dac = false, + .setup = NULL, + .update_trip_temps = NULL, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = { + .ops = &qpnp_tm_gen2_rev2_sensor_ops, + .has_temp_dac = true, + .setup = qpnp_tm_gen2_rev2_init, + .update_trip_temps = qpnp_tm_gen2_rev2_update_trip_temps, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -339,21 +492,27 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) goto out; chip->stage = ret; - stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1 + stage = (chip->subtype == QPNP_TM_SUBTYPE_GEN1) ? chip->stage : alarm_state_map[chip->stage]; if (stage) chip->temp = qpnp_tm_decode_temp(chip, stage); - mutex_unlock(&chip->lock); + if (chip->data->update_trip_temps) { + ret = chip->data->update_trip_temps(chip); + if (ret < 0) + goto out; + } else { + mutex_unlock(&chip->lock); - crit_temp = qpnp_tm_get_critical_trip_temp(chip); + crit_temp = qpnp_tm_get_critical_trip_temp(chip); - mutex_lock(&chip->lock); + mutex_lock(&chip->lock); - ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); - if (ret < 0) - goto out; + ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); + if (ret < 0) + goto out; + } /* Enable the thermal alarm PMIC module in always-on mode. */ reg = ALARM_CTRL_FORCE_ENABLE; @@ -380,6 +539,10 @@ static int qpnp_tm_probe(struct platform_device *pdev) if (!chip) return -ENOMEM; + chip->data = of_device_get_match_data(&pdev->dev); + if (!chip->data) + return -EINVAL; + dev_set_drvdata(&pdev->dev, chip); chip->dev = &pdev->dev; @@ -455,18 +618,21 @@ static int qpnp_tm_probe(struct platform_device *pdev) } chip->subtype = subtype; - if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) + if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major == 1) chip->temp_map = &temp_map_gen2_v1; - else + else if (subtype == QPNP_TM_SUBTYPE_GEN1) chip->temp_map = &temp_map_gen1; + if (chip->data->setup) + chip->data->setup(chip); + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature * before the hardware initialization is completed. */ chip->tz_dev = devm_thermal_of_zone_register( - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); + &pdev->dev, 0, chip, chip->data->ops); if (IS_ERR(chip->tz_dev)) return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev), "failed to register sensor\n"); @@ -488,7 +654,14 @@ static int qpnp_tm_probe(struct platform_device *pdev) } static const struct of_device_id qpnp_tm_match_table[] = { - { .compatible = "qcom,spmi-temp-alarm" }, + { + .compatible = "qcom,spmi-temp-alarm", + .data = &spmi_temp_alarm_data, + }, + { + .compatible = "qcom,spmi-temp-alarm-gen2-rev2", + .data = &spmi_temp_alarm_gen2_rev2_data, + }, { } }; MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);