From patchwork Wed Jul 31 06:18:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 13748118 Received: from mx0.riseup.net (mx0.riseup.net [198.252.153.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E761C1BC40; Wed, 31 Jul 2024 06:19:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.6 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722406769; cv=none; b=V4nFLRNalT0lzezJZB6jl9oIGeEG3W3gimSbPJ1UqRnGC/k2cX6ufkKxMqgis+wFCNrXPNEaK7gQ6iLv/kvjiYdvH5TrBDvglZVWHgNgML/m4vTPKIrU7ajCgmzu7/8SJCyF8j54OsPXq/7lSgFG+q8i035b9z5XoSi4fxOK8NI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722406769; c=relaxed/simple; bh=t36M0udt84hJG27Dr4kbey2RuokqPh+8U3ziWCs6GX4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pkCbB01vx+ldJXTq5/RxdSa0MH/u5yOwmJ9vbFE1rQgtDNMFA34bUpSxlonNO1Bt9yKyNUNkPntKWuRO2v++EE+hXGCSpntt22aUdMHBAtZzMXihWzprh58+tA3MqmT9s5C51P7IQfjCydGmrhe14a4HHE/VaofcpV2NMFHudT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net; spf=pass smtp.mailfrom=riseup.net; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b=W4ZsW6sM; arc=none smtp.client-ip=198.252.153.6 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riseup.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b="W4ZsW6sM" Received: from fews01-sea.riseup.net (fews01-sea-pn.riseup.net [10.0.1.109]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx0.riseup.net (Postfix) with ESMTPS id 4WYhl32bvqz9wV5; Wed, 31 Jul 2024 06:19:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1722406767; bh=t36M0udt84hJG27Dr4kbey2RuokqPh+8U3ziWCs6GX4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=W4ZsW6sMHHPodSXdEaI4jKVtPlWNSCOgLYXWtd98HX+aDNbbxSxahJhIEMxg0QAcG 72kZIYnbPvyotuHBplig4GwXa/08PbBuvapD/vFMq2kz76OfDBuicF6JVVk087D/45 2MSE6DEsQFUavAgOCpbpGpQT+LX9979TiLbYmTFM= X-Riseup-User-ID: 5DEFD3C17A15E45ECEE23306503223ADD9ABCCBFF8AB1C812313B3984F7BE8FD Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews01-sea.riseup.net (Postfix) with ESMTPSA id 4WYhl03q2NzJmtl; Wed, 31 Jul 2024 06:19:24 +0000 (UTC) From: Dang Huynh Date: Wed, 31 Jul 2024 13:18:43 +0700 Subject: [PATCH v3 02/11] arm64: dts: qcom: sm6115-pro1x: Add PCA9534 IO Expander Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-qx1050-feature-expansion-v3-2-b945527fa5d2@riseup.net> References: <20240731-qx1050-feature-expansion-v3-0-b945527fa5d2@riseup.net> In-Reply-To: <20240731-qx1050-feature-expansion-v3-0-b945527fa5d2@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh F(x)tec Pro1X comes with PCA9534 IO Expander, it is used for enabling touch screen VDD/VDDIO and keyboard's caps lock LED. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 70f479a63f2e..47e446249af6 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -70,6 +70,23 @@ &dispcc { status = "disabled"; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + pca9534: gpio@21 { + compatible = "nxp,pca9534"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &pm6125_gpios { vol_up_n: vol-up-n-state { pins = "gpio5"; @@ -89,6 +106,10 @@ &pon_resin { status = "okay"; }; +&qupv3_id_0 { + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm6125-regulators";