[10/10] clk: qcom: camcc-sm8450: Add SM8475 support

Message ID	20240731175919.20333-11-danila@jiaxyga.com (mailing list archive)
State	Superseded
Headers	show Received: from fallback25.i.mail.ru (fallback25.i.mail.ru [79.137.243.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEF231BE25E; Wed, 31 Jul 2024 18:00:08 +0000 (UTC) From: Danila Tikhonov <danila@jiaxyga.com> To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, vkoul@kernel.org, vladimir.zapolskiy@linaro.org, quic_jkona@quicinc.com, dmitry.baryshkov@linaro.org, konradybcio@kernel.org, quic_tdas@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, Danila Tikhonov <danila@jiaxyga.com> Subject: [PATCH 10/10] clk: qcom: camcc-sm8450: Add SM8475 support Date: Wed, 31 Jul 2024 20:59:19 +0300 Message-ID: <20240731175919.20333-11-danila@jiaxyga.com> In-Reply-To: <20240731175919.20333-1-danila@jiaxyga.com> References: <20240731175919.20333-1-danila@jiaxyga.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add SM8475 clock controller drivers \| expand [00/10] Add SM8475 clock controller drivers [01/10] dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings [02/10] clk: qcom: gcc-sm8450: Add SM8475 support [03/10] dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings [04/10] clk: qcom: dispcc-sm8450: Add SM8475 support [05/10] dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings [06/10] clk: qcom: gpucc-sm8450: Add SM8475 support [07/10] dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindings [08/10] clk: qcom: videocc-sm8450: Add SM8475 support [09/10] dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindings [10/10] clk: qcom: camcc-sm8450: Add SM8475 support

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 60e70bf69cb9..7a5d47019a45 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -839,7 +839,7 @@ config SM_CAMCC_8450 depends on ARM64 || COMPILE_TEST select SM_GCC_8450 help - Support for the camera clock controller on SM8450 devices. + Support for the camera clock controller on SM8450 or SM8475 devices. Say Y if you want to support camera devices and camera functionality. config SM_CAMCC_8550 diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c index 26b78eed15ef..75af91fc160f 100644 --- a/drivers/clk/qcom/camcc-sm8450.c +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -54,9 +54,13 @@ static const struct pll_vco rivian_evo_vco[] = { { 864000000, 1056000000, 0 }, }; +static const struct pll_vco rivian_ole_vco[] = { + { 864000000, 1075000000, 0 }, +}; + static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO }; -static const struct alpha_pll_config cam_cc_pll0_config = { +static struct alpha_pll_config cam_cc_pll0_config = { .l = 0x3e, .alpha = 0x8000, .config_ctl_val = 0x20485699, @@ -86,6 +90,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll0_out_even_sm8475_init = { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { .offset = 0x0, .post_div_shift = 10, @@ -109,6 +123,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { { } }; +static struct clk_init_data cam_cc_pll0_out_odd_sm8475_init = { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { .offset = 0x0, .post_div_shift = 14, @@ -127,7 +151,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { }, }; -static const struct alpha_pll_config cam_cc_pll1_config = { +static struct alpha_pll_config cam_cc_pll1_config = { .l = 0x25, .alpha = 0xeaaa, .config_ctl_val = 0x20485699, @@ -157,6 +181,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll1_out_even_sm8475_init = { + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { .offset = 0x1000, .post_div_shift = 10, @@ -175,7 +209,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll2_config = { +static struct alpha_pll_config cam_cc_pll2_config = { .l = 0x32, .alpha = 0x0, .config_ctl_val = 0x90008820, @@ -198,7 +232,7 @@ static struct clk_alpha_pll cam_cc_pll2 = { }, }; -static const struct alpha_pll_config cam_cc_pll3_config = { +static struct alpha_pll_config cam_cc_pll3_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -228,6 +262,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll3_out_even_sm8475_init = { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { .offset = 0x3000, .post_div_shift = 10, @@ -246,7 +290,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll4_config = { +static struct alpha_pll_config cam_cc_pll4_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -276,6 +320,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll4_out_even_sm8475_init = { + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { .offset = 0x4000, .post_div_shift = 10, @@ -294,7 +348,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll5_config = { +static struct alpha_pll_config cam_cc_pll5_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -324,6 +378,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll5_out_even_sm8475_init = { + .name = "cam_cc_pll5_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { .offset = 0x5000, .post_div_shift = 10, @@ -342,7 +406,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll6_config = { +static struct alpha_pll_config cam_cc_pll6_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -372,6 +436,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll6_out_even_sm8475_init = { + .name = "cam_cc_pll6_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { .offset = 0x6000, .post_div_shift = 10, @@ -390,7 +464,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll7_config = { +static struct alpha_pll_config cam_cc_pll7_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -420,6 +494,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll7_out_even_sm8475_init = { + .name = "cam_cc_pll7_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll7.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { .offset = 0x7000, .post_div_shift = 10, @@ -438,7 +522,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll8_config = { +static struct alpha_pll_config cam_cc_pll8_config = { .l = 0x32, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -468,6 +552,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll8_out_even_sm8475_init = { + .name = "cam_cc_pll8_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll8.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { .offset = 0x8000, .post_div_shift = 10, @@ -2817,6 +2911,7 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = { static const struct of_device_id cam_cc_sm8450_match_table[] = { { .compatible = "qcom,sm8450-camcc" }, + { .compatible = "qcom,sm8475-camcc" }, { } }; MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table); @@ -2829,6 +2924,122 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) { + /* Update CAMCC PLL0 Config */ + cam_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll0_config.test_ctl_val = 0x00000000; + cam_cc_pll0_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll0_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll0_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll0_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll0_out_even.clkr.hw.init = &cam_cc_pll0_out_even_sm8475_init; + cam_cc_pll0_out_odd.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll0_out_odd.clkr.hw.init = &cam_cc_pll0_out_odd_sm8475_init; + + /* Update CAMCC PLL1 Config */ + cam_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll1_config.test_ctl_val = 0x00000000; + cam_cc_pll1_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll1_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll1_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll1_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll1_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll1_out_even.clkr.hw.init = &cam_cc_pll1_out_even_sm8475_init; + + /* Update CAMCC PLL2 Config */ + cam_cc_pll2_config.config_ctl_val = 0x10000030; + cam_cc_pll2_config.config_ctl_hi_val = 0x80890263; + cam_cc_pll2_config.user_ctl_val = 0x00000001; + cam_cc_pll2_config.user_ctl_hi_val = 0x00000000; + + cam_cc_pll2.vco_table = rivian_ole_vco; + + /* Update CAMCC PLL3 Config */ + cam_cc_pll3_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll3_config.test_ctl_val = 0x00000000; + cam_cc_pll3_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll3_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll3_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll3_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll3.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll3_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll3_out_even.clkr.hw.init = &cam_cc_pll3_out_even_sm8475_init; + + /* Update CAMCC PLL4 Config */ + cam_cc_pll4_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll4_config.test_ctl_val = 0x00000000; + cam_cc_pll4_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll4_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll4_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll4_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll4_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll4_out_even.clkr.hw.init = &cam_cc_pll4_out_even_sm8475_init; + + /* Update CAMCC PLL5 Config */ + cam_cc_pll5_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll5_config.test_ctl_val = 0x00000000; + cam_cc_pll5_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll5_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll5_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll5_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll5.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll5_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll5_out_even.clkr.hw.init = &cam_cc_pll5_out_even_sm8475_init; + + /* Update CAMCC PLL6 Config */ + cam_cc_pll6_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll6_config.test_ctl_val = 0x00000000; + cam_cc_pll6_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll6_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll6_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll6_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll6.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll6_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll6_out_even.clkr.hw.init = &cam_cc_pll6_out_even_sm8475_init; + + /* Update CAMCC PLL7 Config */ + cam_cc_pll7_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll7_config.test_ctl_val = 0x00000000; + cam_cc_pll7_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll7_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll7_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll7_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll7.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll7_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll7_out_even.clkr.hw.init = &cam_cc_pll7_out_even_sm8475_init; + + /* Update CAMCC PLL8 Config */ + cam_cc_pll8_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll8_config.test_ctl_val = 0x00000000; + cam_cc_pll8_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll8_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll8_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll8_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll8.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll8_out_even.clkr.hw.init = &cam_cc_pll8_out_even_sm8475_init; + } + clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); @@ -2852,5 +3063,5 @@ static struct platform_driver cam_cc_sm8450_driver = { module_platform_driver(cam_cc_sm8450_driver); -MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver"); +MODULE_DESCRIPTION("QCOM CAMCC SM8450 / SM8475 Driver"); MODULE_LICENSE("GPL");

[10/10] clk: qcom: camcc-sm8450: Add SM8475 support

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