| Message ID | 20240731175919.20333-9-danila@jiaxyga.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add SM8475 clock controller drivers | expand |
On Wed, Jul 31, 2024 at 08:59:17PM GMT, Danila Tikhonov wrote: > Add support to the SM8475 video clock controller by extending the > SM8450 video clock controller, which is almost identical but has some > minor differences. > > Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> > --- > drivers/clk/qcom/Kconfig | 2 +- > drivers/clk/qcom/videocc-sm8450.c | 31 ++++++++++++++++++++++++++++--- > 2 files changed, 29 insertions(+), 4 deletions(-) > > @@ -420,6 +421,30 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) > return PTR_ERR(regmap); > } > > + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) { > + /* Update VideoCC PLL0 Config */ > + video_cc_pll0_config.l = 0x1e; > + video_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c; > + video_cc_pll0_config.test_ctl_val = 0x00000000; > + video_cc_pll0_config.test_ctl_hi_val = 0x00000003; > + video_cc_pll0_config.test_ctl_hi1_val = 0x00009000; > + video_cc_pll0_config.test_ctl_hi2_val = 0x00000034; > + video_cc_pll0_config.user_ctl_hi_val = 0x00000005; Maybe it would be better to define new PLL configs rather than to patch the existing ones? > + > + video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; > + > + /* Update VideoCC PLL1 Config */ > + video_cc_pll1_config.l = 0x2b; > + video_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c; > + video_cc_pll1_config.test_ctl_val = 0x00000000; > + video_cc_pll1_config.test_ctl_hi_val = 0x00000003; > + video_cc_pll1_config.test_ctl_hi1_val = 0x00009000; > + video_cc_pll1_config.test_ctl_hi2_val = 0x00000034; > + video_cc_pll1_config.user_ctl_hi_val = 0x00000005; > + > + video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; > + } > + > clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); > clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); > > @@ -445,5 +470,5 @@ static struct platform_driver video_cc_sm8450_driver = { > > module_platform_driver(video_cc_sm8450_driver); > > -MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver"); > +MODULE_DESCRIPTION("QTI VIDEOCC SM8450 / SM8475 Driver"); > MODULE_LICENSE("GPL"); > -- > 2.45.2 >
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index eb2c8db95daf..60e70bf69cb9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1258,7 +1258,7 @@ config SM_VIDEOCC_8450 select QCOM_GDSC help Support for the video clock controller on Qualcomm Technologies, Inc. - SM8450 devices. + SM8450 or SM8475 devices. Say Y if you want to support video devices and functionality such as video encode/decode. endif diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index ed9163d64244..14d18e73332e 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -35,7 +35,7 @@ static const struct pll_vco lucid_evo_vco[] = { { 249600000, 2020000000, 0 }, }; -static const struct alpha_pll_config video_cc_pll0_config = { +static struct alpha_pll_config video_cc_pll0_config = { /* .l includes CAL_L_VAL, L_VAL fields */ .l = 0x0044001e, .alpha = 0x0, @@ -63,7 +63,7 @@ static struct clk_alpha_pll video_cc_pll0 = { }, }; -static const struct alpha_pll_config video_cc_pll1_config = { +static struct alpha_pll_config video_cc_pll1_config = { /* .l includes CAL_L_VAL, L_VAL fields */ .l = 0x0044002b, .alpha = 0xc000, @@ -397,6 +397,7 @@ static struct qcom_cc_desc video_cc_sm8450_desc = { static const struct of_device_id video_cc_sm8450_match_table[] = { { .compatible = "qcom,sm8450-videocc" }, + { .compatible = "qcom,sm8475-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table); @@ -420,6 +421,30 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) return PTR_ERR(regmap); } + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) { + /* Update VideoCC PLL0 Config */ + video_cc_pll0_config.l = 0x1e; + video_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c; + video_cc_pll0_config.test_ctl_val = 0x00000000; + video_cc_pll0_config.test_ctl_hi_val = 0x00000003; + video_cc_pll0_config.test_ctl_hi1_val = 0x00009000; + video_cc_pll0_config.test_ctl_hi2_val = 0x00000034; + video_cc_pll0_config.user_ctl_hi_val = 0x00000005; + + video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + /* Update VideoCC PLL1 Config */ + video_cc_pll1_config.l = 0x2b; + video_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c; + video_cc_pll1_config.test_ctl_val = 0x00000000; + video_cc_pll1_config.test_ctl_hi_val = 0x00000003; + video_cc_pll1_config.test_ctl_hi1_val = 0x00009000; + video_cc_pll1_config.test_ctl_hi2_val = 0x00000034; + video_cc_pll1_config.user_ctl_hi_val = 0x00000005; + + video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + } + clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); @@ -445,5 +470,5 @@ static struct platform_driver video_cc_sm8450_driver = { module_platform_driver(video_cc_sm8450_driver); -MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver"); +MODULE_DESCRIPTION("QTI VIDEOCC SM8450 / SM8475 Driver"); MODULE_LICENSE("GPL");
Add support to the SM8475 video clock controller by extending the SM8450 video clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> --- drivers/clk/qcom/Kconfig | 2 +- drivers/clk/qcom/videocc-sm8450.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-)