Message ID | 20240807-msm-tiling-config-v3-4-ef1bc26efb4c@gmail.com (mailing list archive) |
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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36bbd05980csm16072849f8f.76.2024.08.07.06.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Aug 2024 06:05:14 -0700 (PDT) From: Connor Abbott <cwabbott0@gmail.com> Date: Wed, 07 Aug 2024 14:04:59 +0100 Subject: [PATCH v3 4/4] drm/msm: Fix UBWC macrotile_mode for a680 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240807-msm-tiling-config-v3-4-ef1bc26efb4c@gmail.com> References: <20240807-msm-tiling-config-v3-0-ef1bc26efb4c@gmail.com> In-Reply-To: <20240807-msm-tiling-config-v3-0-ef1bc26efb4c@gmail.com> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Konrad Dybcio <konrad.dybcio@linaro.org>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Marijn Suijten <marijn.suijten@somainline.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Connor Abbott <cwabbott0@gmail.com> X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723035909; l=955; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=/7yQqe2NBmmAI7rwVzTr03fHyeDp7IBl0NXw+ehR9bo=; b=NRs0NJvx7j8M5zqZYO/fc7C48wEQeY0hvIuRQ+ibgD3REpZMOSfpYrZ2wBj5shMArAsIl758E qMPqBlBFximDcNQMDNwJW+j/OoXvlGvDhCiIWPK7t6HjJRfEhX8LT1y X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= |
Series |
drm/msm: Further expose UBWC tiling parameters
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diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 7c2fdd1e7684..7ceca633ceea 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -519,6 +519,9 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a640_family(gpu)) gpu->ubwc_config.amsbc = 1; + if (adreno_is_a680(gpu)) + gpu->ubwc_config.macrotile_mode = 1; + if (adreno_is_a650(gpu) || adreno_is_a660(gpu) || adreno_is_a690(gpu) ||
Make it match the MDSS settings for sc8180x and downstream. Note that without the previous commit that exposes the value of macrotile_mode to mesa, this will break mesa which expects the legacy default value of 0. Therefore we do *not* want to backport it. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ 1 file changed, 3 insertions(+)