| Message ID | 20240809-topic-sl7-v1-3-2090433d8dfc@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | X1E Surface Laptop 7 support | expand |
On Fri, Aug 09, 2024 at 03:43:22AM +0200, Konrad Dybcio wrote: > From: Konrad Dybcio <quic_kdybcio@quicinc.com> > > GENI SE2 within QUP0 is used as UART on some devices, describe it. > > Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 52 ++++++++++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 326283822aee..a2a011702752 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -2142,6 +2142,28 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, > status = "disabled"; > }; > > + uart2: serial@b88000 { > + compatible = "qcom,geni-uart"; > + reg = <0 0x00b88000 0 0x4000>; > + > + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&qup_uart2_default>; > + pinctrl-names = "default"; > + > + status = "disabled"; > + }; > + > spi2: spi@b88000 { > compatible = "qcom,geni-spi"; > reg = <0 0x00b88000 0 0x4000>; > @@ -5365,6 +5387,36 @@ qup_spi23_data_clk: qup-spi23-data-clk-state { > bias-disable; > }; > > + qup_uart2_default: qup-uart2-default-state { > + cts-pins { > + pins = "gpio8"; > + function = "qup0_se2"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + rts-pins { > + pins = "gpio9"; > + function = "qup0_se2"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + tx-pins { > + pins = "gpio10"; > + function = "qup0_se2"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + rx-pins { > + pins = "gpio11"; > + function = "qup0_se2"; > + drive-strength = <2>; > + bias-disable; > + }; Can you combine these into a single entry, i.e. pins = "gpio8", "gpio9", "gpio10", "gpio11"; if they are all the same? Thanks, Stephan
On 9.08.2024 10:41 AM, Stephan Gerhold wrote: > On Fri, Aug 09, 2024 at 03:43:22AM +0200, Konrad Dybcio wrote: >> From: Konrad Dybcio <quic_kdybcio@quicinc.com> >> >> GENI SE2 within QUP0 is used as UART on some devices, describe it. >> >> Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> >> --- [...] > > Can you combine these into a single entry, i.e. > > pins = "gpio8", "gpio9", "gpio10", "gpio11"; > > if they are all the same? Keeping it as-is gives us a) better hw description b) an easier ability to add a label and change e.g. the bias Konrad
On Fri, Aug 09, 2024 at 12:24:03PM +0200, Konrad Dybcio wrote: > On 9.08.2024 10:41 AM, Stephan Gerhold wrote: > > On Fri, Aug 09, 2024 at 03:43:22AM +0200, Konrad Dybcio wrote: > >> From: Konrad Dybcio <quic_kdybcio@quicinc.com> > >> > >> GENI SE2 within QUP0 is used as UART on some devices, describe it. > >> > >> Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> > >> --- > > [...] > > > > > Can you combine these into a single entry, i.e. > > > > pins = "gpio8", "gpio9", "gpio10", "gpio11"; > > > > if they are all the same? > > Keeping it as-is gives us > > a) better hw description > b) an easier ability to add a label and change e.g. the bias > Ok, but it's inconsistent with what we have for qup_uart21_default right now. I think you should either change that as well, or follow the same pattern. :-) Thanks, Stephan
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 326283822aee..a2a011702752 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2142,6 +2142,28 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + uart2: serial@b88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00b88000 0 0x4000>; + + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + spi2: spi@b88000 { compatible = "qcom,geni-spi"; reg = <0 0x00b88000 0 0x4000>; @@ -5365,6 +5387,36 @@ qup_spi23_data_clk: qup-spi23-data-clk-state { bias-disable; }; + qup_uart2_default: qup-uart2-default-state { + cts-pins { + pins = "gpio8"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio10"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + qup_uart21_default: qup-uart21-default-state { /* TX, RX */ pins = "gpio86", "gpio87";