Message ID | 20240821101025.858961-4-amadeus@jmu.edu.cn (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | arm64: dts: qcom: ipq6018: rework CPU Frequency | expand |
On Wed, Aug 21, 2024 at 06:10:24PM GMT, Chukun Pan wrote: > Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 > pmic was never part of the IPQ60xx SoC, it's optional, so we moved > it out of the soc dtsi. > > Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> > --- > arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 + > arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi | 32 ++++++++++++++++++++ Please follow existing examples (msm8916-pm8916.dtsi, msm8916-pm9816.dtsi) and add ipq6018-mp5496.dtsi inheriting ipq6018.dtsi. > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 --------- > 3 files changed, 33 insertions(+), 14 deletions(-) > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > index f5f4827c0e17..e71e8c851246 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > @@ -8,6 +8,7 @@ > /dts-v1/; > > #include "ipq6018.dtsi" > +#include "ipq6018-rdp.dtsi" > > / { > model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; > diff --git a/arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi > new file mode 100644 > index 000000000000..bb56c1245f92 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi > @@ -0,0 +1,32 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * IPQ6018 RDP board common device tree source > + */ > + > +&rpm_requests { > + regulators { > + compatible = "qcom,rpm-mp5496-regulators"; > + > + ipq6018_s2: s2 { > + regulator-min-microvolt = <725000>; > + regulator-max-microvolt = <1062500>; > + regulator-always-on; > + }; > + }; > +}; > + > +&CPU0 { > + cpu-supply = <&ipq6018_s2>; > +}; > + > +&CPU1 { > + cpu-supply = <&ipq6018_s2>; > +}; > + > +&CPU2 { > + cpu-supply = <&ipq6018_s2>; > +}; > + > +&CPU3 { > + cpu-supply = <&ipq6018_s2>; > +}; > diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > index 33062417781a..6f365705e2d8 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > @@ -43,7 +43,6 @@ CPU0: cpu@0 { > clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > clock-names = "cpu"; > operating-points-v2 = <&cpu_opp_table>; > - cpu-supply = <&ipq6018_s2>; > #cooling-cells = <2>; > }; > > @@ -56,7 +55,6 @@ CPU1: cpu@1 { > clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > clock-names = "cpu"; > operating-points-v2 = <&cpu_opp_table>; > - cpu-supply = <&ipq6018_s2>; > #cooling-cells = <2>; > }; > > @@ -69,7 +67,6 @@ CPU2: cpu@2 { > clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > clock-names = "cpu"; > operating-points-v2 = <&cpu_opp_table>; > - cpu-supply = <&ipq6018_s2>; > #cooling-cells = <2>; > }; > > @@ -82,7 +79,6 @@ CPU3: cpu@3 { > clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > clock-names = "cpu"; > operating-points-v2 = <&cpu_opp_table>; > - cpu-supply = <&ipq6018_s2>; > #cooling-cells = <2>; > }; > > @@ -184,16 +180,6 @@ glink-edge { > rpm_requests: rpm-requests { > compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm"; > qcom,glink-channels = "rpm_requests"; > - > - regulators { > - compatible = "qcom,rpm-mp5496-regulators"; > - > - ipq6018_s2: s2 { > - regulator-min-microvolt = <725000>; > - regulator-max-microvolt = <1062500>; > - regulator-always-on; > - }; > - }; > }; > }; > }; > -- > 2.25.1 >
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index f5f4827c0e17..e71e8c851246 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "ipq6018.dtsi" +#include "ipq6018-rdp.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi new file mode 100644 index 000000000000..bb56c1245f92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * IPQ6018 RDP board common device tree source + */ + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; +}; + +&CPU0 { + cpu-supply = <&ipq6018_s2>; +}; + +&CPU1 { + cpu-supply = <&ipq6018_s2>; +}; + +&CPU2 { + cpu-supply = <&ipq6018_s2>; +}; + +&CPU3 { + cpu-supply = <&ipq6018_s2>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 33062417781a..6f365705e2d8 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -43,7 +43,6 @@ CPU0: cpu@0 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -56,7 +55,6 @@ CPU1: cpu@1 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -69,7 +67,6 @@ CPU2: cpu@2 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -82,7 +79,6 @@ CPU3: cpu@3 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -184,16 +180,6 @@ glink-edge { rpm_requests: rpm-requests { compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm"; qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; }; }; };
Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 pmic was never part of the IPQ60xx SoC, it's optional, so we moved it out of the soc dtsi. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 + arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi | 32 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 --------- 3 files changed, 33 insertions(+), 14 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-rdp.dtsi