| Message ID | 20240823-x1e80100-phy-add-gen4x4-v3-1-b7765631ca01@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | phy: qcom: qmp-pcie: Add support for Gen4 4-lane mode for X1E80100 | expand |
On Fri, Aug 23, 2024 at 10:04:15AM GMT, Abel Vesa wrote: > The sixth PCIe instance on X1E80100 can be used in either 4-lane mode or > 2-lane mode. Document the 4-lane mode as a separate compatible. As the patches were merged, it's too late for this series, but as a note: we should think of a way to describe the PHY configuration without changing the compatibility strings. The hardware stays the same, it's just the number of lanes being wired that changes. The obvious way to handle platform-specific differences is by using num-lanes property of the PCIe host and then passing required configuration (num lanes, max speed, etc.) to the PCIe PHY via phy_configure() call. > > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > index 03dbd02cf9e7..dcf4fa55fbba 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > @@ -40,6 +40,7 @@ properties: > - qcom,sm8650-qmp-gen4x2-pcie-phy > - qcom,x1e80100-qmp-gen3x2-pcie-phy > - qcom,x1e80100-qmp-gen4x2-pcie-phy > + - qcom,x1e80100-qmp-gen4x4-pcie-phy > > reg: > minItems: 1 > @@ -118,6 +119,7 @@ allOf: > contains: > enum: > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > + - qcom,x1e80100-qmp-gen4x4-pcie-phy > then: > properties: > reg: > @@ -169,6 +171,7 @@ allOf: > - qcom,sc8280xp-qmp-gen3x1-pcie-phy > - qcom,sc8280xp-qmp-gen3x2-pcie-phy > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > + - qcom,x1e80100-qmp-gen4x4-pcie-phy > then: > properties: > clocks: > > -- > 2.34.1 >
On Fri, Aug 30, 2024 at 01:42:10PM +0300, Dmitry Baryshkov wrote: > On Fri, Aug 23, 2024 at 10:04:15AM GMT, Abel Vesa wrote: > > The sixth PCIe instance on X1E80100 can be used in either 4-lane mode or > > 2-lane mode. Document the 4-lane mode as a separate compatible. > > As the patches were merged, it's too late for this series, but as a > note: we should think of a way to describe the PHY configuration without > changing the compatibility strings. The hardware stays the same, it's > just the number of lanes being wired that changes. No, this is not about configuration and we need two separate compatibles as the two PHY instances are distinct and only one of them can be used in 4-lane mode. The mistake was to ever describe pcie6a as 2-lane in the x1e80100 dtsi (and possibly also in the ambiguous commit message above). Whether pcie6a is used in 4-lane or 2-lane mode is determined by a TCSR register. Johan
On Fri, 30 Aug 2024 at 15:09, Johan Hovold <johan@kernel.org> wrote: > > On Fri, Aug 30, 2024 at 01:42:10PM +0300, Dmitry Baryshkov wrote: > > On Fri, Aug 23, 2024 at 10:04:15AM GMT, Abel Vesa wrote: > > > The sixth PCIe instance on X1E80100 can be used in either 4-lane mode or > > > 2-lane mode. Document the 4-lane mode as a separate compatible. > > > > As the patches were merged, it's too late for this series, but as a > > note: we should think of a way to describe the PHY configuration without > > changing the compatibility strings. The hardware stays the same, it's > > just the number of lanes being wired that changes. > > No, this is not about configuration and we need two separate compatibles > as the two PHY instances are distinct and only one of them can be used > in 4-lane mode. Ack, makes sense. > The mistake was to ever describe pcie6a as 2-lane in the x1e80100 dtsi > (and possibly also in the ambiguous commit message above). Whether > pcie6a is used in 4-lane or 2-lane mode is determined by a TCSR > register. Yes, I was confused by the commit message. I assumed that the compatible string is used to switch PHY modes. Had the patchset come with the DT patch, it would be easier to understand what was going on.
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 03dbd02cf9e7..dcf4fa55fbba 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -40,6 +40,7 @@ properties: - qcom,sm8650-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen3x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy reg: minItems: 1 @@ -118,6 +119,7 @@ allOf: contains: enum: - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy then: properties: reg: @@ -169,6 +171,7 @@ allOf: - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy then: properties: clocks: