| Message ID | 20240827063631.3932971-3-quic_qianyu@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On 27.08.2024 8:36 AM, Qiang Yu wrote: > x1e80100 SoC uses QMP phy with version v6.30 for PCIe Gen4 x8. Add the new > PCS offsets in a dedicated header file. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h > new file mode 100644 > index 000000000000..9aa6d3622c24 > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved. > + */ > + > +#ifndef QCOM_PHY_QMP_PCS_V6_30_H_ > +#define QCOM_PHY_QMP_PCS_V6_30_H_ > + > +/* Only for QMP V6_30 PHY - PCIe PCS registers */ > +#define QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2 0x0cc > +#define QPHY_V6_30_PCS_G3S2_PRE_GAIN 0x17c > +#define QPHY_V6_30_PCS_RX_SIGDET_LVL 0x194 > +#define QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7 0x1dc > +#define QPHY_V6_30_PCS_TX_RX_CONFIG 0x1e0 > +#define QPHY_V6_30_PCS_TX_RX_CONFIG2 0x1e4 > +#define QPHY_V6_30_PCS_EQ_CONFIG4 0x1fc > +#define QPHY_V6_30_PCS_EQ_CONFIG5 0x200 Squash with the previous one and the next one, and please make the indentation consistent Konrad
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h new file mode 100644 index 000000000000..9aa6d3622c24 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_30_H_ +#define QCOM_PHY_QMP_PCS_V6_30_H_ + +/* Only for QMP V6_30 PHY - PCIe PCS registers */ +#define QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2 0x0cc +#define QPHY_V6_30_PCS_G3S2_PRE_GAIN 0x17c +#define QPHY_V6_30_PCS_RX_SIGDET_LVL 0x194 +#define QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7 0x1dc +#define QPHY_V6_30_PCS_TX_RX_CONFIG 0x1e0 +#define QPHY_V6_30_PCS_TX_RX_CONFIG2 0x1e4 +#define QPHY_V6_30_PCS_EQ_CONFIG4 0x1fc +#define QPHY_V6_30_PCS_EQ_CONFIG5 0x200 + +#endif
x1e80100 SoC uses QMP phy with version v6.30 for PCIe Gen4 x8. Add the new PCS offsets in a dedicated header file. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h