From patchwork Fri Aug 30 08:11:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 13784509 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88551158A37; Fri, 30 Aug 2024 08:12:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725005552; cv=none; b=U4Qua+CrodgDqD92YJBTskf/bAEpGQntnRwpjOq1xIxB44sKP5x1TFn6wxBgOMZwX8jS/vfLDqNkQxUXu1Z/VqKjGZE2sJxVi4vPI4dl9wCnjpec37GAX1hYrDzbdwlSJ3DIi59ycda9u/kpt2M8D5u5aV2bzkSglF3byBkfKU0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725005552; c=relaxed/simple; bh=LAh247OMXBxLcP2w6rrXfbIsVsDYtTMFsNBITfnYw54=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VJ+eTvA7pFrLMRfw5iiwavxW4c8ewPVi88mkcf6g9d1QAmkNPFZymggHZo7jkY30scUIkQ3fwporQImf2IR/VXwn5O8Ntn+dzbI9bJIMctSvvnL7AXf510M1ua8iRUYImKH8+NtAXvPgzXB1bBBdDsQhqYnA/OQtU1+Bg3P3W3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=M/cL4aF2; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="M/cL4aF2" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47U7onoF028379; Fri, 30 Aug 2024 08:12:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= nJ6+DSpczrnSs4I88jN8J93McBZVjZyaOHjkWS6Q2jw=; b=M/cL4aF2P9sNpgjr 9ejR9EZPtQAQub1VCBg+wf3BZnKUHU4Y9hyCUchMnqH3f+kgVto2faBtu4F1lkia qkDnXBaLKm8QepBiq0KD22rmFf5pblI3eJz41R51N0ez/wYrAkEzlsfHHPMrg92A jUsogrNJADzHIh4K8XP9R78LAREkROflkIXuAByeOAyonilYEKQzHtT0ZhmGdOPD v7saqP+5EOAoOCJswgZpqdzjlO0GxB6eYE/yfjSd2Do/iRHLUwJ624VF6licydqA VElCYys6LWSFqrTSNjL5NvjPvgHpQzRHaWhiRlAiRolco8ieFeHELz9TRqNOM7jJ U5DTGQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419puuftu8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 Aug 2024 08:12:05 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47U8C45t021440 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 Aug 2024 08:12:04 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 Aug 2024 01:11:58 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 2/6] dt-bindings: PCI: qcom: Add IPQ5108 SoC Date: Fri, 30 Aug 2024 13:41:28 +0530 Message-ID: <20240830081132.4016860-3-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240830081132.4016860-1-quic_srichara@quicinc.com> References: <20240830081132.4016860-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ftw1_vdWFsNhwYgKOuYpUsBIRuCD_JOW X-Proofpoint-ORIG-GUID: Ftw1_vdWFsNhwYgKOuYpUsBIRuCD_JOW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-30_04,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408300060 From: Nitheesh Sekar Add support for the PCIe controller on the Qualcomm IPQ5108 SoC to the bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran --- [v3] No change .../devicetree/bindings/pci/qcom,pcie.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index f867746b1ae5..c12efa27b8d8 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -312,6 +313,39 @@ allOf: - const: ahb # AHB reset - const: phy_ahb # PHY AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5018 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_bridge # AXI bridge clock + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core sticky reset + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_s_sticky # AXI slave sticky reset + - if: properties: compatible: @@ -503,6 +537,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074