| Message ID | 20240830133908.2246139-2-quic_mojha@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 1a82fbfc87fd7627ce9499590fb381069db99e8f |
| Headers | show |
| Series | [v2,1/2] dt-bindings: mfd: qcom,tcsr: Add compatible for sa8775p | expand |
On Fri, Aug 30, 2024 at 07:09:08PM +0530, Mukesh Ojha wrote: > Enable download mode for sa8775p which can help collect > ramdump for this SoC. > > Reviewed-by: Elliot Berman <quic_eberman@quicinc.com> > Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com> > --- Looks like, this got missed to be picked while its binding is merged. -Mukesh > Changes in v2: > - Added R-by tag and rebased it. > > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index e8dbc8d820a6..fa057073ee2d 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -281,6 +281,7 @@ eud_in: endpoint { > firmware { > scm { > compatible = "qcom,scm-sa8775p", "qcom,scm"; > + qcom,dload-mode = <&tcsr 0x13000>; > memory-region = <&tz_ffi_mem>; > }; > }; > @@ -3072,6 +3073,11 @@ tcsr_mutex: hwlock@1f40000 { > #hwlock-cells = <1>; > }; > > + tcsr: syscon@1fc0000 { > + compatible = "qcom,sa8775p-tcsr", "syscon"; > + reg = <0x0 0x1fc0000 0x0 0x30000>; > + }; > + > gpucc: clock-controller@3d90000 { > compatible = "qcom,sa8775p-gpucc"; > reg = <0x0 0x03d90000 0x0 0xa000>; > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index e8dbc8d820a6..fa057073ee2d 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -281,6 +281,7 @@ eud_in: endpoint { firmware { scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; memory-region = <&tz_ffi_mem>; }; }; @@ -3072,6 +3073,11 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "qcom,sa8775p-tcsr", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x30000>; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sa8775p-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>;