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[4/4] soc: qcom: llcc: Add llcc configuration support for the QCS8300 platform

Message ID 20240903-qcs8300_llcc_driver-v1-4-228659bdf067@quicinc.com (mailing list archive)
State Changes Requested
Headers show
Series soc: qcom: llcc: Add llcc support for the QCS8300 platform | expand

Commit Message

Jingyi Wang Sept. 3, 2024, 6:21 a.m. UTC 
Add llcc configuration support for the QCS8300 platform.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
 drivers/soc/qcom/llcc-qcom.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Krzysztof Kozlowski Sept. 3, 2024, 7:14 a.m. UTC | #1 
On Tue, Sep 03, 2024 at 02:21:32PM +0800, Jingyi Wang wrote:
> Add llcc configuration support for the QCS8300 platform.

It is LLCC. Fix it everywhere and create commits using consisting style.
In some subjects you call it LLCC but here llcc...

> 
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>

Best regards,
Krzysztof
Jingyi Wang Sept. 3, 2024, 7:18 a.m. UTC | #2 
On 9/3/2024 3:14 PM, Krzysztof Kozlowski wrote:
> On Tue, Sep 03, 2024 at 02:21:32PM +0800, Jingyi Wang wrote:
>> Add llcc configuration support for the QCS8300 platform.
> 
> It is LLCC. Fix it everywhere and create commits using consisting style.
> In some subjects you call it LLCC but here llcc...
> 
well noted, will fix that.
>>
>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> 
> Best regards,
> Krzysztof
> 
Thanks,
Jingyi
diff mbox series

Patch

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 3fb45e625d82..571fb6045f25 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -422,6 +422,14 @@  static const struct llcc_slice_config sm8650_data[] = {
 	{LLCC_VIDVSP,   28,  256, 3, 1, 0xFFFFFF, 0x0,      0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 };
 
+static struct llcc_slice_config qcs8300_data[] =  {
+	{LLCC_GPUHTW,   11, 128, 1, 1, 0x00F, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_GPU,      12, 512, 1, 1, 0x00F, 0x0, 0, 0, 0, 1, 0, 1, 0},
+	{LLCC_MMUHWT,   13, 128, 1, 1, 0x00F, 0x0, 0, 0, 0, 0, 1, 0, 0},
+	{LLCC_ECC,      26, 256, 3, 1, 0x00F, 0x0, 0, 0, 0, 0, 1, 0, 0},
+	{LLCC_WRCACHE,	31, 128, 1, 1, 0x00F, 0x0, 0, 0, 0, 0, 1, 0, 0},
+};
+
 static const struct llcc_slice_config qdu1000_data_2ch[] = {
 	{ LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
 	{ LLCC_MODHW,    9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
@@ -539,6 +547,16 @@  static const u32 llcc_v2_1_reg_offset[] = {
 	[LLCC_COMMON_STATUS0]	= 0x0003400c,
 };
 
+static const struct qcom_llcc_config qcs8300_cfg[] = {
+	{
+		.sct_data	= qcs8300_data,
+		.size		= ARRAY_SIZE(qcs8300_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+};
+
 static const struct qcom_llcc_config qdu1000_cfg[] = {
 	{
 		.sct_data       = qdu1000_data_8ch,
@@ -721,6 +739,11 @@  static const struct qcom_llcc_config x1e80100_cfg[] = {
 	},
 };
 
+static const struct qcom_sct_config qcs8300_cfgs = {
+	.llcc_config	= qcs8300_cfg,
+	.num_config	= ARRAY_SIZE(qcs8300_cfg),
+};
+
 static const struct qcom_sct_config qdu1000_cfgs = {
 	.llcc_config	= qdu1000_cfg,
 	.num_config	= ARRAY_SIZE(qdu1000_cfg),
@@ -1380,6 +1403,7 @@  static int qcom_llcc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_llcc_of_match[] = {
+	{ .compatible = "qcom,qcs8300-llcc", .data = &qcs8300_cfgs},
 	{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
 	{ .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs },
 	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },