From patchwork Fri Sep 6 13:13:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13794167 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E428D1552FA; Fri, 6 Sep 2024 13:14:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725628499; cv=none; b=L/vlu+7RfrcQt4szig1uA5whmGFNc0o4RmHxIM3ljR1yKDmaJfodS+tgo+Jhl78e4oc/wF4bXaHxk+PhympfmRY43U5UJbN8C+dnYq0oW6WGFu980SV+Q3TCxkc4XabS+H+yd9WtrE0dboRn9CTdlSkuNU2Jg2UPf552lD++E7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725628499; c=relaxed/simple; bh=5fUaH2KILQJGIGQcOFDUoLlj/mM8Dq86b5IxB3kE0zo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=F/tDZgRIzHIjylmzuQKDb9I72Z17df7T2d8oBUgXjM9QkYmoF+Xwtn2t/OFdxoMFSZ5pJUQ7Szwd3lowGxqmdyxtRemGmwYmcbScHcQSnIglcD0qep4hPzcCgI/S10lD4cIwYQ1itqSjkKjfiYzzm/dFG7EhT+6zmQNccRr/KDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AYAI+WSV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AYAI+WSV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8DAA9C4CEC4; Fri, 6 Sep 2024 13:14:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725628498; bh=5fUaH2KILQJGIGQcOFDUoLlj/mM8Dq86b5IxB3kE0zo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AYAI+WSVWf/7374y+wuTTM4G4aVA0YmqBWdZAhkJZBsqM/q97g8z5aFK0KZpll3Wd 4F4VTKV6r9JliGfjiaALWZw/TjlXfeYeQnsxpSN8S7vLBLGwcfnYxqVHLrANvzGBmg 1vP2hjYigawxTCyl9tuOWRa6x5wTjIoqRjhgK2l48FRaWIuImyFuCth/rzbdFi+HqF LWrK/QPw1zR7X8//QdeiTk6tlWDZ3Qk99hEQznT2Y4qDg4/cfsWI5d9PXHn5xm0CnB em44e1+BOgy/gdphqTUDRdEDFgrh3tdPU163Irn+akFxuTQ+oQ5Y7YK75tn3x9uZ83 ycEj5MmHerOrQ== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1smYo3-000000006Ag-1JEG; Fri, 06 Sep 2024 15:15:19 +0200 From: Johan Hovold To: Greg Kroah-Hartman Cc: Jiri Slaby , Bjorn Andersson , Konrad Dybcio , Douglas Anderson , =?utf-8?q?N=C3=ADcolas_F_=2E_R_?= =?utf-8?q?=2E_A_=2E_Prado?= , linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v2 3/8] soc: qcom: geni-se: add GP_LENGTH/IRQ_EN_SET/IRQ_EN_CLEAR registers Date: Fri, 6 Sep 2024 15:13:31 +0200 Message-ID: <20240906131336.23625-4-johan+linaro@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240906131336.23625-1-johan+linaro@kernel.org> References: <20240906131336.23625-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Douglas Anderson For UART devices the M_GP_LENGTH is the TX word count. For other devices this is the transaction word count. For UART devices the S_GP_LENGTH is the RX word count. The IRQ_EN set/clear registers allow you to set or clear bits in the IRQ_EN register without needing a read-modify-write. Acked-by: Bjorn Andersson Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20240610152420.v4.1.Ife7ced506aef1be3158712aa3ff34a006b973559@changeid Tested-by: Nícolas F. R. A. Prado Signed-off-by: Johan Hovold --- include/linux/soc/qcom/geni-se.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 0f038a1a0330..c3bca9c0bf2c 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -88,11 +88,15 @@ struct geni_se { #define SE_GENI_M_IRQ_STATUS 0x610 #define SE_GENI_M_IRQ_EN 0x614 #define SE_GENI_M_IRQ_CLEAR 0x618 +#define SE_GENI_M_IRQ_EN_SET 0x61c +#define SE_GENI_M_IRQ_EN_CLEAR 0x620 #define SE_GENI_S_CMD0 0x630 #define SE_GENI_S_CMD_CTRL_REG 0x634 #define SE_GENI_S_IRQ_STATUS 0x640 #define SE_GENI_S_IRQ_EN 0x644 #define SE_GENI_S_IRQ_CLEAR 0x648 +#define SE_GENI_S_IRQ_EN_SET 0x64c +#define SE_GENI_S_IRQ_EN_CLEAR 0x650 #define SE_GENI_TX_FIFOn 0x700 #define SE_GENI_RX_FIFOn 0x780 #define SE_GENI_TX_FIFO_STATUS 0x800 @@ -101,6 +105,8 @@ struct geni_se { #define SE_GENI_RX_WATERMARK_REG 0x810 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 #define SE_GENI_IOS 0x908 +#define SE_GENI_M_GP_LENGTH 0x910 +#define SE_GENI_S_GP_LENGTH 0x914 #define SE_DMA_TX_IRQ_STAT 0xc40 #define SE_DMA_TX_IRQ_CLR 0xc44 #define SE_DMA_TX_FSM_RST 0xc58 @@ -234,6 +240,9 @@ struct geni_se { #define IO2_DATA_IN BIT(1) #define RX_DATA_IN BIT(0) +/* SE_GENI_M_GP_LENGTH and SE_GENI_S_GP_LENGTH fields */ +#define GP_LENGTH GENMASK(31, 0) + /* SE_DMA_TX_IRQ_STAT Register fields */ #define TX_DMA_DONE BIT(0) #define TX_EOT BIT(1)