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Wed, 11 Sep 2024 08:03:45 GMT Received: from jingyw-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 01:03:41 -0700 From: Jingyi Wang Date: Wed, 11 Sep 2024 16:03:15 +0800 Subject: [PATCH v2 1/4] dt-bindings: qcom,pdc: document QCS8300 Power Domain Controller Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240911-qcs8300_binding-v2-1-de8641b3eaa1@quicinc.com> References: <20240911-qcs8300_binding-v2-0-de8641b3eaa1@quicinc.com> In-Reply-To: <20240911-qcs8300_binding-v2-0-de8641b3eaa1@quicinc.com> To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Robert Marko CC: , , , , , , Jingyi Wang X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726041816; l=943; i=quic_jingyw@quicinc.com; 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PDC is included in QCS8300 SoC. This controller acts as an interrupt controller, enabling the detection of interrupts when the GIC is non-operational. Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 985fa10abb99..acd6341e9f90 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,qcs8300-pdc - qcom,qdu1000-pdc - qcom,sa8775p-pdc - qcom,sc7180-pdc