| Message ID | 20240919-qcs615-clock-driver-v1-2-51c0cc92e3a2@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add GCC and RPMH clock controller for QCS615 SoC | expand |
On 19/09/2024 09:32, Taniya Das wrote: > Add the RPMHCC clocks required for QCS615 SoC. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > drivers/clk/qcom/clk-rpmh.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index 4acde937114a..96600aba9bf2 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -795,6 +795,24 @@ static const struct clk_rpmh_desc clk_rpmh_x1e80100 = { > .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks), > }; > > +static struct clk_hw *qcs615_rpmh_clocks[] = { > + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, > + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, > + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, > + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, > + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, > + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, > + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, > + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, > + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, > + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, > +}; > + > +static const struct clk_rpmh_desc clk_rpmh_qcs615 = { > + .clks = qcs615_rpmh_clocks, > + .num_clks = ARRAY_SIZE(qcs615_rpmh_clocks), > +}; > + > static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, > void *data) > { > @@ -879,6 +897,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) > > static const struct of_device_id clk_rpmh_match_table[] = { > { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, > + { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, Keep alphabetical order, by compatible. Best regards, Krzysztof
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 4acde937114a..96600aba9bf2 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -795,6 +795,24 @@ static const struct clk_rpmh_desc clk_rpmh_x1e80100 = { .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks), }; +static struct clk_hw *qcs615_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_qcs615 = { + .clks = qcs615_rpmh_clocks, + .num_clks = ARRAY_SIZE(qcs615_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -879,6 +897,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, + { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
Add the RPMHCC clocks required for QCS615 SoC. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- drivers/clk/qcom/clk-rpmh.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)