diff mbox series

[RFC,04/11] arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu

Message ID 20240919-topic-apps_smmu_coherent-v1-4-5b3a8662403d@quicinc.com (mailing list archive)
State Accepted
Commit 2b73b83cb82aefb6c907ea91a9977641bbcae683
Headers show
Series Affirm SMMU coherent pagetable walker capability on RPMh SoCs | expand

Commit Message

Konrad Dybcio Sept. 18, 2024, 10:57 p.m. UTC 
From: Konrad Dybcio <quic_kdybcio@quicinc.com>

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 80a57aa228397e23e3e2d5643c0b563a60d71170..d36f677ae4cd857388dcd5821160a6472a0904b4 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -5008,6 +5008,7 @@  apps_smmu: iommu@15000000 {
 				     <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
 		};
 
 		intc: interrupt-controller@17a00000 {