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[RFC,08/11] arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu

Message ID 20240919-topic-apps_smmu_coherent-v1-8-5b3a8662403d@quicinc.com (mailing list archive)
State Accepted
Commit 05bd9923d15e8508cd0fa4f3d03437df1a9362aa
Headers show
Series Affirm SMMU coherent pagetable walker capability on RPMh SoCs | expand

Commit Message

Konrad Dybcio Sept. 18, 2024, 10:57 p.m. UTC 
From: Konrad Dybcio <quic_kdybcio@quicinc.com>

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 27f87835bc5595f5023319f77878a8ea4090a3f6..28e57ad885f4f64abbf429c337d45504ff2830ad 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -4296,6 +4296,7 @@  apps_smmu: iommu@15000000 {
 				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
 		};
 
 		remoteproc_adsp: remoteproc@17300000 {