| Message ID | 20240924-preemption-a750-t-v5-10-0be2bf81c187@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Preemption support for A7XX | expand |
nit, lowercase "a6xx" in subject prefix (no need to resend just for this, I can fix it up when applying patches if needed.. but if you do resend pls fix that) BR -R On Tue, Sep 24, 2024 at 4:30 AM Antonino Maniscalco <antomani103@gmail.com> wrote: > > Initialize with 4 rings to enable preemption. > > For now only on A750 as other targets require testing. > > Add the "preemption_enabled" module parameter to override this for other > A7xx targets. > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK > Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 3 ++- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- > drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + > 4 files changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 316f23ca91671d973797f2a5b69344f376707325..0e3041b2941905f1acdc9e571e0549a960a7edfa 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1240,7 +1240,8 @@ static const struct adreno_info a7xx_gpus[] = { > .gmem = 3 * SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > - ADRENO_QUIRK_HAS_HW_APRIV, > + ADRENO_QUIRK_HAS_HW_APRIV | > + ADRENO_QUIRK_PREEMPTION, > .init = a6xx_gpu_init, > .zapfw = "gen70900_zap.mbn", > .a6xx = &(const struct a6xx_info) { > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index edbcb6d229ba614be910ee70e75731538116e4a4..4760f9469613c0bf208f56be9608747b5aa75606 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -2529,6 +2529,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > struct a6xx_gpu *a6xx_gpu; > struct adreno_gpu *adreno_gpu; > struct msm_gpu *gpu; > + extern int enable_preemption; > bool is_a7xx; > int ret; > > @@ -2567,7 +2568,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > return ERR_PTR(ret); > } > > - if (is_a7xx) > + if ((enable_preemption == 1) || (enable_preemption == -1 && > + (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) > + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); > + else if (is_a7xx) > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); > else if (adreno_has_gmu_wrapper(adreno_gpu)) > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index cfc74a9e2646d3de76a06bd67457d69afa49e309..9ffe91920fbfb4841b28aabec9fbde94539fdd83 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -20,6 +20,10 @@ bool allow_vram_carveout = false; > MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); > module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); > > +int enable_preemption = -1; > +MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=on , 0=disable, -1=auto (default))"); > +module_param(enable_preemption, int, 0600); > + > extern const struct adreno_gpulist a2xx_gpulist; > extern const struct adreno_gpulist a3xx_gpulist; > extern const struct adreno_gpulist a4xx_gpulist; > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 87098567483b69c21025b80f356e0a68f0e7f172..d1cd53f05de68b3873f35520655e09e82fc40449 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -56,6 +56,7 @@ enum adreno_family { > #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) > #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) > #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) > +#define ADRENO_QUIRK_PREEMPTION BIT(5) > > /* Helper for formating the chip_id in the way that userspace tools like > * crashdec expect. > > -- > 2.46.1 >
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 316f23ca91671d973797f2a5b69344f376707325..0e3041b2941905f1acdc9e571e0549a960a7edfa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1240,7 +1240,8 @@ static const struct adreno_info a7xx_gpus[] = { .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, .init = a6xx_gpu_init, .zapfw = "gen70900_zap.mbn", .a6xx = &(const struct a6xx_info) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index edbcb6d229ba614be910ee70e75731538116e4a4..4760f9469613c0bf208f56be9608747b5aa75606 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2529,6 +2529,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; + extern int enable_preemption; bool is_a7xx; int ret; @@ -2567,7 +2568,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } - if (is_a7xx) + if ((enable_preemption == 1) || (enable_preemption == -1 && + (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); + else if (is_a7xx) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index cfc74a9e2646d3de76a06bd67457d69afa49e309..9ffe91920fbfb4841b28aabec9fbde94539fdd83 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -20,6 +20,10 @@ bool allow_vram_carveout = false; MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); +int enable_preemption = -1; +MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=on , 0=disable, -1=auto (default))"); +module_param(enable_preemption, int, 0600); + extern const struct adreno_gpulist a2xx_gpulist; extern const struct adreno_gpulist a3xx_gpulist; extern const struct adreno_gpulist a4xx_gpulist; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 87098567483b69c21025b80f356e0a68f0e7f172..d1cd53f05de68b3873f35520655e09e82fc40449 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -56,6 +56,7 @@ enum adreno_family { #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) +#define ADRENO_QUIRK_PREEMPTION BIT(5) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect.