diff mbox series

[3/3] arm64: dts: qcom: sc7280: Add cpucp mbox node

Message ID 20240924050941.1251485-4-quic_kshivnan@quicinc.com (mailing list archive)
State Changes Requested
Headers show
Series qcom: sc7280: Enable cpucp mbox | expand

Commit Message

Shivnandan Kumar Sept. 24, 2024, 5:09 a.m. UTC 
Add the CPUCP mailbox node required for communication with CPUCP.

Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

--
2.25.1

Comments

Krzysztof Kozlowski Sept. 25, 2024, 2:22 p.m. UTC | #1 
On 24/09/2024 07:09, Shivnandan Kumar wrote:
> Add the CPUCP mailbox node required for communication with CPUCP.
> 
> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 3d8410683402..4b9b26a75c62 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -4009,6 +4009,14 @@ gem_noc: interconnect@9100000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
> 
> +		cpucp_mbox: mailbox@17430000 {

Are you sure you placed it in correct location (the order is by unit
address, see DTS coding style).

> +			compatible = "qcom,sc7280-cpucp-mbox";
> +			reg = <0 0x18590000 0 0x2000>,
> +			      <0 0x17C00000 0 0x10>;

Lowercase hex... we just fixed it everywhere and you introduce again
same issues.



Best regards,
Krzysztof
Shivnandan Kumar Oct. 3, 2024, 5:41 a.m. UTC | #2 
On 9/25/2024 7:52 PM, Krzysztof Kozlowski wrote:
> On 24/09/2024 07:09, Shivnandan Kumar wrote:
>> Add the CPUCP mailbox node required for communication with CPUCP.
>>
>> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 3d8410683402..4b9b26a75c62 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -4009,6 +4009,14 @@ gem_noc: interconnect@9100000 {
>>   			qcom,bcm-voters = <&apps_bcm_voter>;
>>   		};
>>
>> +		cpucp_mbox: mailbox@17430000 {
> 
> Are you sure you placed it in correct location (the order is by unit
> address, see DTS coding style).
> 

I will correct it in next series.


>> +			compatible = "qcom,sc7280-cpucp-mbox";
>> +			reg = <0 0x18590000 0 0x2000>,
>> +			      <0 0x17C00000 0 0x10>;
> 
> Lowercase hex... we just fixed it everywhere and you introduce again
> same issues.
>


ACK

> 
> 
> Best regards,
> Krzysztof
>
Bjorn Andersson Oct. 6, 2024, 2:35 a.m. UTC | #3 
On Tue, Sep 24, 2024 at 10:39:41AM GMT, Shivnandan Kumar wrote:
> Add the CPUCP mailbox node required for communication with CPUCP.

I'd like to see a description of why that's useful...

But perhaps more importantly, why are there no user(s) of this?

Regards,
Bjorn

> 
> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 3d8410683402..4b9b26a75c62 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -4009,6 +4009,14 @@ gem_noc: interconnect@9100000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
> 
> +		cpucp_mbox: mailbox@17430000 {
> +			compatible = "qcom,sc7280-cpucp-mbox";
> +			reg = <0 0x18590000 0 0x2000>,
> +			      <0 0x17C00000 0 0x10>;
> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +			#mbox-cells = <1>;
> +		};
> +
>  		system-cache-controller@9200000 {
>  			compatible = "qcom,sc7280-llcc";
>  			reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
> --
> 2.25.1
>
Shivnandan Kumar Oct. 17, 2024, 11:51 a.m. UTC | #4 
On 10/6/2024 8:05 AM, Bjorn Andersson wrote:
> On Tue, Sep 24, 2024 at 10:39:41AM GMT, Shivnandan Kumar wrote:
>> Add the CPUCP mailbox node required for communication with CPUCP.
> 
> I'd like to see a description of why that's useful...
> 

I will add in next patch set.

> But perhaps more importantly, why are there no user(s) of this?
> 

We will later add features such as BUS DCVS (memlat algorithm in CPUCP) 
and CPUCP logging based on this series.

> Regards,
> Bjorn
> 


>>
>> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 3d8410683402..4b9b26a75c62 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -4009,6 +4009,14 @@ gem_noc: interconnect@9100000 {
>>   			qcom,bcm-voters = <&apps_bcm_voter>;
>>   		};
>>
>> +		cpucp_mbox: mailbox@17430000 {
>> +			compatible = "qcom,sc7280-cpucp-mbox";
>> +			reg = <0 0x18590000 0 0x2000>,
>> +			      <0 0x17C00000 0 0x10>;
>> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> +			#mbox-cells = <1>;
>> +		};
>> +
>>   		system-cache-controller@9200000 {
>>   			compatible = "qcom,sc7280-llcc";
>>   			reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
>> --
>> 2.25.1
>>
Konrad Dybcio Oct. 17, 2024, 9:13 p.m. UTC | #5 
On 17.10.2024 1:51 PM, Shivnandan Kumar wrote:
> 
> 
> On 10/6/2024 8:05 AM, Bjorn Andersson wrote:
>> On Tue, Sep 24, 2024 at 10:39:41AM GMT, Shivnandan Kumar wrote:
>>> Add the CPUCP mailbox node required for communication with CPUCP.
>>
>> I'd like to see a description of why that's useful...
>>
> 
> I will add in next patch set.
> 
>> But perhaps more importantly, why are there no user(s) of this?
>>
> 
> We will later add features such as BUS DCVS (memlat algorithm in CPUCP) and CPUCP logging based on this series.

I think Bjorn's question here is also "what kind of boards is this going
to be useful on", especially given 7280 was more or less released in
basically all firmware flavors that we make..

Konrad
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 3d8410683402..4b9b26a75c62 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -4009,6 +4009,14 @@  gem_noc: interconnect@9100000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};

+		cpucp_mbox: mailbox@17430000 {
+			compatible = "qcom,sc7280-cpucp-mbox";
+			reg = <0 0x18590000 0 0x2000>,
+			      <0 0x17C00000 0 0x10>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			#mbox-cells = <1>;
+		};
+
 		system-cache-controller@9200000 {
 			compatible = "qcom,sc7280-llcc";
 			reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,