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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-537a864d937sm156713e87.273.2024.09.24.03.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 03:06:14 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/9] arm64: dts: qcom: sm8450-qrd: explicitly disable dispcc on the board Date: Tue, 24 Sep 2024 13:05:55 +0300 Message-ID: <20240924100602.3813725-3-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240924100602.3813725-1-vladimir.zapolskiy@linaro.org> References: <20240924100602.3813725-1-vladimir.zapolskiy@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A platform display clock controller is expected to be enabled by default for all boards, however in particular cases preset display clock setting is expected. To avoid any probable regression before enabling display clock controller for all SM8450 platforms disable it for SM8450-QRD board only. Signed-off-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 7b62ead68e77..8c39fbcaad80 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -349,6 +349,10 @@ vreg_l6e_1p2: ldo6 { }; }; +&dispcc { + status = "disabled"; +}; + &pcie0 { status = "okay"; };