From patchwork Thu Sep 26 06:54:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lijuan Gao X-Patchwork-Id: 13812886 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 696601A4B80; Thu, 26 Sep 2024 06:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333745; cv=none; b=G0R9o09Z9rD/ekECq+UaquJP890cbUrZrP1KH6ZyZwXpFeWSOOgFQTmeyem1LpjhhBJpeYZSFf5GUFASm983WhNEKlMIPwUrY0HBpD58zRoyXb59l0GPc2oYWbK2L2fUpLZ5fFlWfPWwsDpZi+zUyJR5qrzZnk11ZbTKXSvqp5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333745; c=relaxed/simple; bh=xxwXitskCsakF/qCZJEqZAA31USkl0hjaEN4KrBg0hI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=DBWGf9C5GdFd66vv9yYF3qHSi/A3ZAExTTkncWLiteQKVUbv4jC39DAT6FrRWvkiYKL+BRi34/LYZbCDbqnl1Cx7srCjgbRjb8iVI8o1dibqTX5yjeC8jpOR1zHeazCF6twksolow7OayoLGDsmPhX2ySZBD6sKOdA/vo6fKBPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=YIDqIrCd; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="YIDqIrCd" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48PH5HJq024190; Thu, 26 Sep 2024 06:55:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= GEIp388/DE4pBQf4egikwq/BjLVrUcJcWKKsYbY9JRw=; b=YIDqIrCdbvK5rO2Q QFhQh0sE9Z4sgz6wG3fLMZ1dGX64wMHpflGTZGC5tY+yjewfBGNpMVVvC5LlnVe4 Wb2iDaBD8AN4iEsYY02APfEcxe7i5Vy1n7ST1kIW/i1BZ6OFL5/TyDOp8/jMzB/y zTlCPrY6UgUc0wG0PIvxCyBsCAqq/bm0xSluMDhJGtrGQd7Dxro4drSQpU9W/73A C+QwuMp+i2czBw3SL9lbH8rbc1PQ0MzA/6ZnlYfFH2IamJIfczaAUpZM0iYKqc5N q57z/Ifme7duPrx9Aiqqdp3y28mQQbjiEb3Eb+xGgyIffdQqqK76+SW7+rhgfaFv SzEF0A== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41spwexacd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:36 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6tZ3i025456 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:35 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:55:28 -0700 From: Lijuan Gao Date: Thu, 26 Sep 2024 14:54:47 +0800 Subject: [PATCH v3 7/7] arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS615 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240926-add_initial_support_for_qcs615-v3-7-e37617e91c62@quicinc.com> References: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> In-Reply-To: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727333702; l=1429; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=xxwXitskCsakF/qCZJEqZAA31USkl0hjaEN4KrBg0hI=; b=1YCY5X16pS8znV6g54YI2IubtsRyf61+FCIYu6S4vgTY/O3T4saD4h6KQqncbOPztr/Lkx853 hsEObmY4gnZAhhkC8yKNzzhXbdFR6W5K/HF2+odlabsVZh012XdycJw X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Tybk08A8YWJ6X48OMDEYSwb4VrQi3pLO X-Proofpoint-ORIG-GUID: Tybk08A8YWJ6X48OMDEYSwb4VrQi3pLO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 mlxscore=0 mlxlogscore=700 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260043 Enable clock controller, interconnect and pinctrl for Qualcomm QCS615 platform to boot to UART console. The serial engine depends on gcc, interconnect and pinctrl. Since the serial console driver is only available as built-in, so these configs needs be built-in for the UART device to probe and register the console. Signed-off-by: Lijuan Gao --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5fdbfea7a5b2..c066fe3a32c3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -607,6 +607,7 @@ CONFIG_PINCTRL_MSM8996=y CONFIG_PINCTRL_MSM8998=y CONFIG_PINCTRL_QCM2290=y CONFIG_PINCTRL_QCS404=y +CONFIG_PINCTRL_QCS615=y CONFIG_PINCTRL_QDF2XXX=y CONFIG_PINCTRL_QDU1000=y CONFIG_PINCTRL_SA8775P=y @@ -1323,6 +1324,7 @@ CONFIG_MSM_MMCC_8998=m CONFIG_QCM_GCC_2290=y CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_GCC_404=y +CONFIG_QCS_GCC_615=y CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m CONFIG_SC_DISPCC_7280=m @@ -1625,6 +1627,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y CONFIG_INTERCONNECT_QCOM_OSM_L3=m CONFIG_INTERCONNECT_QCOM_QCM2290=y CONFIG_INTERCONNECT_QCOM_QCS404=m +CONFIG_INTERCONNECT_QCOM_QCS615=y CONFIG_INTERCONNECT_QCOM_QDU1000=y CONFIG_INTERCONNECT_QCOM_SA8775P=y CONFIG_INTERCONNECT_QCOM_SC7180=y