| Message ID | 20241001-wrapped-keys-dts-v7-2-a668519b7ffe@linaro.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | arm64: dts: qcom: extend the register range for ICE on sm8[56]50 | expand |
On 01/10/2024 10:35, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > The Inline Crypto Engine (ICE) for UFS/EMMC supports the Hardware Key > Manager (HWKM) to securely manage storage keys. Enable using this > hardware on sm8550. > > This requires us to increase the register range: HWKM is an additional > piece of hardware sitting alongside ICE, and extends the old ICE's > register space. > > NOTE: Although wrapped keys cannot be independently generated and > tested on this platform using generate, prepare and import key calls, > there are non-kernel paths to create wrapped keys, and still use the > kernel to program them into ICE. Hence, enabling wrapped key support > on sm8550 too. > > Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> > Co-developed-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 9dc0ee3eb98f..93c8aa32e411 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -2076,7 +2076,8 @@ opp-300000000 { > ice: crypto@1d88000 { > compatible = "qcom,sm8550-inline-crypto-engine", > "qcom,inline-crypto-engine"; > - reg = <0 0x01d88000 0 0x8000>; > + reg = <0 0x01d88000 0 0x18000>; > + > clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > }; > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 1.10.2024 10:35 AM, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > The Inline Crypto Engine (ICE) for UFS/EMMC supports the Hardware Key > Manager (HWKM) to securely manage storage keys. Enable using this > hardware on sm8550. > > This requires us to increase the register range: HWKM is an additional > piece of hardware sitting alongside ICE, and extends the old ICE's > register space. > > NOTE: Although wrapped keys cannot be independently generated and > tested on this platform using generate, prepare and import key calls, > there are non-kernel paths to create wrapped keys, and still use the > kernel to program them into ICE. Hence, enabling wrapped key support > on sm8550 too. > > Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> > Co-developed-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9dc0ee3eb98f..93c8aa32e411 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2076,7 +2076,8 @@ opp-300000000 { ice: crypto@1d88000 { compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; };