| Message ID | 20241001113738.152467-1-quic_vpernami@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | bus: mhi: host: pci_generic: Add support for QDU100 device | expand |
On Tue, Oct 01, 2024 at 05:07:35PM +0530, Vivek Pernamitta wrote: > Add MHI controller configuration for QDU100 device. > > This Qualcomm QDU100 device is inline accelerator card > which is an extension to QRU100 5G RAN platform. > which is designed to simplify 5G deployments by offering > a turnkey solution for ease of deployment with O-RAN > fronthaul and 5G NR layer 1 High (L1 High) processing, > and to accelerate operator and infrastructure vendor > adoption of virtualized RAN platforms. > > https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qualcomm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf > Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> > --- > drivers/bus/mhi/host/pci_generic.c | 49 ++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c > index 9938bb034c1c..1153697fa858 100644 > --- a/drivers/bus/mhi/host/pci_generic.c > +++ b/drivers/bus/mhi/host/pci_generic.c > @@ -245,6 +245,52 @@ struct mhi_pci_dev_info { > .channel = ch_num, \ > } > > +static const struct mhi_channel_config modem_qcom_qdu100_mhi_channels[] = { > + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), > + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), > + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), > + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), > + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), > + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), > + MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), > + MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), > + MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), > + MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), > + MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), > + MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), > + MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), > + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), > + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), > + MHI_CHANNEL_CONFIG_UL(48, "IP_SW1", 256, 6), > + MHI_CHANNEL_CONFIG_DL(49, "IP_SW1", 256, 6), > + MHI_CHANNEL_CONFIG_UL(50, "IP_SW2", 256, 7), > + MHI_CHANNEL_CONFIG_DL(51, "IP_SW2", 256, 7), I believe you are going to add support for these channels in mhi_net driver. If so, it would be good to mention that in the commit message as these channels won't be useable for now. > +}; > + > +static struct mhi_event_config modem_qcom_qdu100_mhi_events[] = { > + /* first ring is control+data ring */ > + MHI_EVENT_CONFIG_CTRL(0, 64), > + /* SAHARA dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(1, 256), > + /* Software channels dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(2, 64), > + MHI_EVENT_CONFIG_SW_DATA(3, 256), > + MHI_EVENT_CONFIG_SW_DATA(4, 256), > + /* Software IP channels dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(5, 512), > + MHI_EVENT_CONFIG_SW_DATA(6, 512), > + MHI_EVENT_CONFIG_SW_DATA(7, 512), > +}; > + > +static const struct mhi_controller_config modem_qcom_qdu100_mhi_config = { > + .max_channels = 128, > + .timeout_ms = 120000, > + .num_channels = ARRAY_SIZE(modem_qcom_qdu100_mhi_channels), > + .ch_cfg = modem_qcom_qdu100_mhi_channels, > + .num_events = ARRAY_SIZE(modem_qcom_qdu100_mhi_events), > + .event_cfg = modem_qcom_qdu100_mhi_events, > +}; > + Where is the 'mhi_pci_dev_info' struct? > static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { > MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), > MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), > @@ -822,6 +868,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { > /* NETPRISMA FCUN69 (SDX6X) */ > { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), > .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, > + /* QDU100, x100-DU */ > + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), > + .driver_data = (kernel_ulong_t)&modem_qcom_qdu100_mhi_config }, Why are you passing 'mhi_controller_config' instead of 'mhi_pci_dev_info'? - Mani
On Tue, Oct 01, 2024 at 05:07:35PM GMT, Vivek Pernamitta wrote: > Add MHI controller configuration for QDU100 device. > > This Qualcomm QDU100 device is inline accelerator card > which is an extension to QRU100 5G RAN platform. > which is designed to simplify 5G deployments by offering > a turnkey solution for ease of deployment with O-RAN > fronthaul and 5G NR layer 1 High (L1 High) processing, > and to accelerate operator and infrastructure vendor > adoption of virtualized RAN platforms. Please replace marketing text with a sensible description. > > https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qualcomm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf There is a tag for this, it's even called 'Link:' > Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> > --- > drivers/bus/mhi/host/pci_generic.c | 49 ++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) >
diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index 9938bb034c1c..1153697fa858 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -245,6 +245,52 @@ struct mhi_pci_dev_info { .channel = ch_num, \ } +static const struct mhi_channel_config modem_qcom_qdu100_mhi_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), + MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), + MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), + MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), + MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), + MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), + MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), + MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), + MHI_CHANNEL_CONFIG_UL(48, "IP_SW1", 256, 6), + MHI_CHANNEL_CONFIG_DL(49, "IP_SW1", 256, 6), + MHI_CHANNEL_CONFIG_UL(50, "IP_SW2", 256, 7), + MHI_CHANNEL_CONFIG_DL(51, "IP_SW2", 256, 7), +}; + +static struct mhi_event_config modem_qcom_qdu100_mhi_events[] = { + /* first ring is control+data ring */ + MHI_EVENT_CONFIG_CTRL(0, 64), + /* SAHARA dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(1, 256), + /* Software channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(2, 64), + MHI_EVENT_CONFIG_SW_DATA(3, 256), + MHI_EVENT_CONFIG_SW_DATA(4, 256), + /* Software IP channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(5, 512), + MHI_EVENT_CONFIG_SW_DATA(6, 512), + MHI_EVENT_CONFIG_SW_DATA(7, 512), +}; + +static const struct mhi_controller_config modem_qcom_qdu100_mhi_config = { + .max_channels = 128, + .timeout_ms = 120000, + .num_channels = ARRAY_SIZE(modem_qcom_qdu100_mhi_channels), + .ch_cfg = modem_qcom_qdu100_mhi_channels, + .num_events = ARRAY_SIZE(modem_qcom_qdu100_mhi_events), + .event_cfg = modem_qcom_qdu100_mhi_events, +}; + static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), @@ -822,6 +868,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* NETPRISMA FCUN69 (SDX6X) */ { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, + /* QDU100, x100-DU */ + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), + .driver_data = (kernel_ulong_t)&modem_qcom_qdu100_mhi_config }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
Add MHI controller configuration for QDU100 device. This Qualcomm QDU100 device is inline accelerator card which is an extension to QRU100 5G RAN platform. which is designed to simplify 5G deployments by offering a turnkey solution for ease of deployment with O-RAN fronthaul and 5G NR layer 1 High (L1 High) processing, and to accelerate operator and infrastructure vendor adoption of virtualized RAN platforms. https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qualcomm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> --- drivers/bus/mhi/host/pci_generic.c | 49 ++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+)