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[93.89.166.199]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cb66a654b9sm2366497a12.34.2024.10.21.13.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 13:22:29 -0700 (PDT) From: Gabor Juhos Date: Mon, 21 Oct 2024 22:21:59 +0200 Subject: [PATCH 3/5] clk: qcom: gcc-ipq6018: remove alpha values from NSS Crypto PLL's config Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241021-alpha-mode-cleanup-v1-3-55df8ed73645@gmail.com> References: <20241021-alpha-mode-cleanup-v1-0-55df8ed73645@gmail.com> In-Reply-To: <20241021-alpha-mode-cleanup-v1-0-55df8ed73645@gmail.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.14.2 Since both the 'alpha' and 'alpha_hi' members of the configuration is initialized with zero values, the output rate of the PLL will be the same whether alpha mode is enabled or not. Remove the initialization of the alpha* members to make it clear that alpha mode is not required to get the desired output rate. While at it, also add a comment to indicate the frequency the PLL runs at with the current configuration. No functional changes, the PLL runs at 1.2 GHz both before and after the change. Tested on Xiaomi Mi Router AX1800 (IPQ6018, out-of-tree board). Signed-off-by: Gabor Juhos --- drivers/clk/qcom/gcc-ipq6018.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index ab0f7fc665a9790dd8edba0cf4b86c5c672a337d..d861191b0c85ccc105ac0e62d7a68210c621fc13 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -4194,10 +4194,9 @@ static const struct alpha_pll_config ubi32_pll_config = { .test_ctl_hi_val = 0x4000, }; +/* 1200 MHz configuration */ static const struct alpha_pll_config nss_crypto_pll_config = { .l = 0x32, - .alpha = 0x0, - .alpha_hi = 0x0, .config_ctl_val = 0x4001055b, .main_output_mask = BIT(0), .pre_div_val = 0x0, @@ -4206,7 +4205,6 @@ static const struct alpha_pll_config nss_crypto_pll_config = { .post_div_mask = GENMASK(11, 8), .vco_mask = GENMASK(21, 20), .vco_val = 0x0, - .alpha_en_mask = BIT(24), }; static struct clk_hw *gcc_ipq6018_hws[] = {