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Wed, 23 Oct 2024 06:24:17 GMT Received: from hu-mohs-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Oct 2024 23:24:10 -0700 From: Mohammad Rafi Shaik To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Bard Liao , Jaroslav Kysela , "Takashi Iwai" CC: Pierre-Louis Bossart , Sanyog Kale , , , , , , , Mohammad Rafi Shaik Subject: [RESEND v2 1/4] ASoC: dt-bindings: wcd937x-sdw: Add static channel mapping support Date: Wed, 23 Oct 2024 11:53:28 +0530 Message-ID: <20241023062331.3872883-2-quic_mohs@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241023062331.3872883-1-quic_mohs@quicinc.com> References: <20241023062331.3872883-1-quic_mohs@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Hr9BX4W0TTFSr8f0K9UaAAeCbHF9Wnj0 X-Proofpoint-ORIG-GUID: Hr9BX4W0TTFSr8f0K9UaAAeCbHF9Wnj0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 impostorscore=0 mlxscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410230037 Add static channel mapping between master and slave rx/tx ports for Qualcomm wcd937x soundwire codec. Currently, the channel mask for each soundwire port is hardcoded in the wcd937x-sdw driver, and the same channel mask value is configured in the soundwire master. The Qualcomm boards like the QCM6490-IDP require different channel mask settings for the soundwire master and slave ports. With the introduction of the following channel mapping properties, it is now possible to configure the master channel mask directly from the device tree. The qcom,tx-channel-mapping property specifies the static channel mapping between the slave and master tx ports in the order of slave port channels which is adc1, adc2, adc3, adc4, dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. The qcom,rx-channel-mapping property specifies static channel mapping between the slave and master rx ports in the order of slave port channels which is hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. Signed-off-by: Mohammad Rafi Shaik --- .../bindings/sound/qcom,wcd937x-sdw.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml index d3cf8f59cb23..a6bc9b391db0 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml @@ -58,6 +58,38 @@ properties: items: enum: [1, 2, 3, 4, 5] + qcom,tx-channel-mapping: + description: | + Specifies static channel mapping between slave and master tx port + channels. + In the order of slave port channels which is adc1, adc2, adc3, adc4, + dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. + ch_mask1 ==> bit mask value 1 + ch_mask2 ==> bit mask value 2 + ch_mask3 ==> bit mask value 4 + ch_mask4 ==> bit mask value 8 + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 8 + maxItems: 13 + items: + enum: [1, 2, 4, 8] + + qcom,rx-channel-mapping: + description: | + Specifies static channels mapping between slave and master rx port + channels. + In the order of slave port channels, which is + hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. + ch_mask1 ==> bit mask value 1 + ch_mask2 ==> bit mask value 2 + ch_mask3 ==> bit mask value 4 + ch_mask4 ==> bit mask value 8 + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 8 + maxItems: 8 + items: + enum: [1, 2, 4, 8] + required: - compatible - reg @@ -74,6 +106,8 @@ examples: compatible = "sdw20217010a00"; reg = <0 4>; qcom,rx-port-mapping = <1 2 3 4 5>; + qcom,rx-channel-mapping = /bits/ 8 <0x01 0x02 0x01 0x01 0x02 + 0x01 0x01 0x02>; }; }; @@ -85,6 +119,8 @@ examples: compatible = "sdw20217010a00"; reg = <0 3>; qcom,tx-port-mapping = <2 2 3 4>; + qcom,tx-channel-mapping = /bits/ 8 <0x01 0x02 0x01 0x01 0x02 0x04 + 0x04 0x08 0x01 0x02 0x04 0x8>; }; };